HC15 (2003)

General Information

HOT CHIPS 15 (2003)
Date August 17-19, 2003
Place Memorial Auditorium, Stanford University
Program Final Program PDF
Committees Organizing and Program Committees

Tutorials

Tutorials Sunday, August 17, 2003
Morning Tutorial Test and Reliability Techniques for Robust System Design
Chair: Tadao Nakamura (Tohoku University)
Speakers: Subhasish Mitra (Intel)
Afternoon Tutorial Past and Future of Cryptographic Engineering
Chair: John Wawrzynek (UC Berkeley)
Speakers: Christof Paar (Ruhr-Universitaet Bochum)

Conference Day One

Session Monday, August 18, 2003
Opening Remarks Siamak Arya (Telairity), General Chair
Pradeep Dubey (Intel), Program Co-Chairs
Mike Flynn (Stanford)
Session 1 Supercomputing
Chair: John Sell (AMD)
Red Storm: A 10,000 node system with reliable, high bandwidth, low latency interconnect, Bob Alverson (Cray) PDFQuadrics QsNet II : A Network for Supercomputing Applications, Fabrizio Petrini, David Addison, Jon Beecroft, David Hewson, Moray McLaren (Los Alamos) PDF

Sub-lithographic Semiconductor Computing Systems, Andre DeHon (Caltech) PDF

Keynote 1 Chair: Mike Flynn (Stanford)Keynote: The Whole Earth Simulator: World’s Fastest Supercomputer, Tadashi Watanabe (NEC) PDF
Session 2 Embedded
Chair: Howard Sachs (Telairity)
A Multithreaded RISC/DSP Proc. w/ High Speed Interconnect, Erik Norden (Infineon) PDFIntelligent Energy Management: an SoC Design Based on ARM926EJ-S, David Flynn (ARM) PDF
Session 3 Application Specific Chips
Chair: Henry Moreton (NVIDIA)RAMP-IV: A Low-Power / High-Performance 2D/3D Graphics Accelerator for Mobile Multimedia Applications, Ramchan Woo, Sungdae Choi, Ju-Ho Sohn, Seong-Jun Song, Yong-Don Bae, and Hoi-Jun Yo (KAIST) PDFTMS320DM310: A Portable Digital Media Processor, Deepu Talla, Russ Austen, Dave Brier, Ching-Yu Hung, Derek Huynh, David Smith, Bruce Xiong, Raj Talluri, and Frank Brill (Texas Instruments) PDF

ReX: A dNTSC Receiver System on Chip, Slobodan Simovich (Dotcast) PDF

Session 4 Wireless
Chair: Keith Diefendorff (MIPS)The Architecture of the Intel® PXA800F Cellular Processor, Dilip Krishnaswamy (Intel) PDFBCM2132: GSM/GPRS Handset Baseband w/ Integrated EDGE & Media Functions, Nelson Sollenberger, Li Fun Chang, Paul Lu (Broadcom)PDF

Broadcom WLAN chipset for 802.11 a/b/g, Jason A. Trachewsky, Arya Behzad, Reza Rofougaran (Broadcom) PDF

A UMTS Baseband Receiver Chip for Infrastructure Applications, Sundararajan Sriram, K. Brown, P. Bertrand, F. Moerman, O. Paviot, C. Sengupta, V. Sundararajan, A. Gatherer (Texas Instruments) PDF

Panel Discussion Disasters I Have Been Involved With
Moderator: Nick Tredennick (Editor, Gilder Technology Report) PDFPanelists:
Bob Cousins (CTO, Storfinity) PDF
Dave Wyland (The Wyland Group, Inc.) PDF
Jack D. Grimes (Consultant) PDF
Jim Turley (Editor, Silicon Insider) PDF

Conference Day Two

Session Tuesday, August 19, 2003
Session 5 Switching and Routing
Chair: Marc Tremblay (Sun)A Single Chip Shared Mem Switch w/ Twelve 10Gb Ethernet Ports, Takeshi Shimizu, Yukihiro Nakagawa, Sridhar Pathi, Yasushi Umezawa, Takashi Miyoshi, Takeshi Horie, Akira Hattori (Fujitsu) PDFTerabit Crossbar Switch Core for Multi-Clock-Domain SoCs, Uri Cummings (Fulcrum) PDF

Adaptive Packet Processor, Bill Lynch (Procket) PDF

Session 6 Security
Chair: Pradeep Dubey (Intel)Multi-Gigabit SSL & TLS Record Layer Protocol Processor and Multi-Gigabit IPSec Processor, David Chin, Terry Tham (Broadcom) PDFContinuum Security Processor: Micro-Architecture Overview, Srinivas Mantripragada (NetContinuum) PDF

Nitrox-II™ Inline Security Processor, M. Raghib Hussain (Cavium) PDF

Keynote 2 Chair: Alan Smith (UC Berkeley)Perspectives on the Future of Microelectronics for Military Systems
Robert F. Leheny Director, Microsystems Technology Office (DARPA)
Session 7 Potpourri
Chair: Forest Baskett (NEA)Ubicom MASI – Wireless Network Processor, David Fotland (Ubicom) PDFA 10 Gbps Ethernet TCP/IP Processor, Jianping Xu, Nitin Borkar, Vasantha Erraguntla, Yatin Hoskote, Tanay Karnik, Sriram Vangal, Justin Rattne (Intel) PDF

Janus: A Gigaflop VLIW+RISC SoC Tile, Pier Stanislao Paolucci (Atmel) PDF

Session 8 Processors
Chair: John Crawford (Intel)An Embedded 600Mhz Synthesized Processor, Howard Sachs (Telairity) PDFPOWER5: IBM’s Next Generation POWER Microprocessor, Ron Kalla (IBM) PDF

Ultrasparc Gemini: Dual CPU Processor, Sanjiv Kapil (Sun) PDF

Two New 130nm Itanium 2 Processors for 2003, Harry Muljono, Stefan Rusu (Intel) PDF

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