HC18 (2006)

General Information

Hot Chips 18 (2006)

Date August 20-22, 2006
Place Memorial Auditorium, Stanford University
Committees Organizing and Program Committees


TutorialsSunday, August 20, 2006

Morning Tutorial Moderator: Christos Kozyrakis (Stanford University)

  • Multicore Programming: From Threads to Transactional Memory 
    Yuan Lin (Sun Microsystems) PDF, Ali-Reza Adl-Tabatabai (Intel) PDF, Bratin Saha (Intel) PDF, and Christos Kozyrakis (Stanford University)PDF
Afternoon Tutorial Moderator: Jan Rabaey

  • Wireless in the Home: Challenges and Opportunities PDF

Conference Day One

SessionMonday, August 21, 2006

Opening Remarks Opening remarks
Session 1 Video Processing 
Chair: Howard Sachs, Telairity
• Highly Integrated Nexperia PNX8535 Hybrid Television ProcessorPhilips Semiconductors PDF
Authors(s): Ben Pronk• Heterogeneous Multiprocessing for Efficient Multi-Standard High Definition Video Decoding, Philips Semiconductors PDF
Authors(s): Stephane Mutz, Philippe Durieux

• Home entertainment-quality multimedia experience whilst on the move – Philips Nexperia Mobile Multimedia Co-Processor PNX4103, Philips Semiconductors PDF
Authors(s): Marcin Klecha, Ralf Karge, Richard O’Connor

Keynote 1 Cool Codes for Hot Chips PDF
 Pradeep Dubey, Intel
Author(s): Justin Rattner, Chief Technology Officer & Intel Senior Fellow (Intel)
Session 2 Microprocessors I 
Chair: Marc Tremblay, Sun Microsystems
• The Low-Power High-Performance Architecture of the PWRficient Processor Family, P.A. Semi PDF
Author(s): Tse-Yu Yeh• The Opteron CMP NorthBridge Architecture, Now and in the Future, AMD PDF
Author(s): Pat Conway, Bill Hughes
Session 3 Memory and Storage 
Chair: Mitsuo Saito, Toshiba• Z-RAM Ultra-dense Memory for 90nm and Below, Innovative Silicon PDF
Author(s): David Fisch, Anant Singh, Greg Popov• The Ultra Small HDD for the Mobile Applications, Toshiba PDF
Author(s): Akihiko Takeo, Kazuhito Shimomura, Jun Itoh
Session 4 Reconfigurable Computing 
Chair: John Wawrzynek, UC Berkeley• Virtex5, the Next Generation 65nm FPGA, Xilinx PDF
Author(s): Steve Douglass, Peter Alfke, Kees Vissers• RAMP: Research Accelerator for Multiple Processors PDF
Author(s): Professor David Patterson (UC Berkeley), Professor Arvind (MIT), Professor Krste Asanovic (MIT), Professor Derek Chiou (UT Austin), Professor James C. Hoe (CMU), Professor Christoforos Kozyrakis (Stanford), Shih-Lien Lu (Intel), Professor Mark Oskin (U Washington), Professor Jan Rabaey (UC Berkeley), and Professor John Wawrzynek (UC Berkeley)

• An Implementation of Hardware Accelerator using Dynamically Reconfigurable Architecture, Toshiba R&D Center PDF
Author(s): Takashi Yoshikawa, Yutaka Yamada, Shigehiro Asano

Session 5 Parallel Processing 
Chair: John Wawrzynek, UC Berkeley• TeraOPS Hardware & Software: A New Massively-Parallel, MIMD Computing Fabric IC, Ambric PDF
Author(s): Mike Butts, Anthony Mark Jones• The CA1024: A Fully Programmable System-On-Chip for Cost-Effective HDTV Media Processing, Connex Technology PDF
Author(s): Gheorghe Stefan, Lazar Bivolarski, Anand Sheel, Bogdan Mitu, Tom Thomson, and Dan Tomescu

• Hardware and Applications of AsAP: An Asynchronous Array of Simple Processors, UC Davis PDF QT QT
Author(s): Bevan Baas (Professor, Electrical and Computer Engineering, UC Davis), Zhiyi Yu, Michael Meeuwsen, Omar Sattari, Ryan Apperson, Eric Work, Jeremy Webb, Michael Lai, Daniel Gurman, Chi Chen, Jason Cheung, Dean Truong, Tinoosh Mohsenin (UC Davis)

Panel Discussion Who Owns the Living Room?
Moderator: Jan-Willem van de Waerdt, Philips SemiconductorsPanelists:James Akiyama (IntelPDF, Bob Brummer (MicrosoftPDF, Bill Curtis (DellPDF, Eugene Shteyn (Philips CE), Alan Messer (SamsungPDF, Glen Stone (SonyPDF, Prof. Yamada (Kyushu Institute of TechnologyPDF

Conference Day Two

SessionTuesday, August 16, 2006


Session 6 Embedded Processors 
Chair: Chuck Moore, AMD• ARM996HS: The First Licensable, Clockless 32-bit Processor Core, Handshake Solutions PDF
Author(s): Arjan Bink (Handshake Solutions), Richard York (ARM Ltd.), Mark de Clercq (Handshake Solutions)• The MIPS32® 34K™ Processor Cores: Ultimate Design Flexibility for Embedded Applications, MIPS PDF
Author(s): Ryan Kinter

• Design of a Reusable 1GHz, Super-scalar ARM Processor, ARM Inc. PDF
Author(s): Stephen Hill

• Towards Optimal Custom Instruction Processors, Imperial College, London PDF
Author(s): Wayne Luk, Oskar Mencer, Robert G. Dimond, Kubilay Atasu

Keynote 2 Collaborative Innovation: A New Lever in Information Technology Development PDF
 Forest Baskett, New Enterprise AssociatesAuthor(s): Bernard Meyerson, IBM Fellow; VP Strategic Alliances and Chief Technologist, Meyerson IBM Systems & Technology Group, Development
Session 7 Novel Silicon Applications 
Chair: Rajeevan Amirtharajah, UC Davis• In Silico Vox: Towards Speech Recognition in Silicon, Carnegie Mellon University PDF WMV
Author(s): Professor Rob A. Rutenbar (ECE & CS), Edward C. Lin, Kai Yu, Tsuhan Chen• A Novel Processor Architecture for High-Performance Stream Processing, IBM Research, Zurich PDF
Author(s): Jan van Lunteren

• Micro Manipulator Array for Nano-bioelectrics Era, Toshiba R&D Center PDF QT QTQT QT QT
Author(s): Hideyuki Funaki, Kazuhiro Suzuki, Yujiro Naruse, Kazuhiko Itaya, Shuichi Uchikoga

Session 8 Communications
Chair: Forest Baskett, New Enterprise Associates• FocalPoint: A Low-Latency, High-Bandwidth Ethernet Switch Chip, Fulcrum Microsystems PDF
Author(s): Uri Cummings• SH-MobileG1: A Single-Chip Application and Dual-mode Baseband Processor,Renesas Technology PDF
Author(s): Masayuki Ito, Takahiro Irita, Eiji Yamamoto, Kunihiko Nishiyama, Takao Koike, Yoshihiko Tsuchihashi, Hiroyuki Asano, Hiroshi Yagi, Saneaki Tamaki, Ken Tatezawa, Toshihiro Hattori, Shinichi Yoshioka (Renesas Technology), and Koji Ohno (NTT DoCoMo)

• APP300 Access Network Processor, Agere Systems PDF
Author(s): Balakrishnan Sundararaman

Session 9 Microprocessors II 
Chair: Alan Smith, UC Berkeley• TULSA, A Dual P4 Core Large Shared Cache Intel® Xeon™ Processor for the MP Server Market Segment, Intel PDF
Author(s): Jeffrey D. Gilbert, Stephen H. Hunt, Daniel Gunadi, and Ganapati Srinivasa• Niagara2: A Highly-Threaded Server-on-A-Chip, Sun Microsystems PDF
Author(s): Greg Grohoski

• Blackford: A Dual Processor Chipset for Servers and Workstations, Intel PDF
Author(s): Kai cheng, Sundaram Chinthamani, Sivakumar Radhakrishnan, Fayé Briggs and Kathy Debnath

• Inside the Core™ Microarchitecture, Intel PDF
Author(s): Jack Doweck