HC26 (2014)

Flint Center, Cupertino, CA, Sunday-Tuesday, August 10-12, 2014.

TutorialsConf. Day1Conf. Day2Posters

Tutorials

Sun 8/10 Tutorial Title Presenter Affiliation
8:00 AM Breakfast
9:00 AM Emerging Trends in HW Support for Security Welcome and Introduction John Davis
9:05 AM Security Basics Ruby Lee Princeton
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9:50 AM Mobile HW Security Vikas Chandra ARM
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10:35 AM Secure Systems Design Leendert Van Doorn AMD
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11:20 AM Break
11:35 AM Mitigating Exploits, Rootkits and Advanced Persistent Threats David Durham Intel
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12:20 AM University Research in Hardware Security Ruby Lee Princeton
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12:50 PM Q&A / Wrap-up All speakers

1:00 PM Lunch
2:00 PM Internet of Things Welcome Behnam Robatmili
2:10 PM Powering the Internet of Things Yogesh Ramadass TI
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3:00 Ultra Low Power Design Approaches for IoT Massimo Alioto National University of Singapore
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3:50 PM Break
4:00 PM Connecting the Internet of Everything Michael Stauffer Qualcomm
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4:50 PM Standards for Constrained IoT Devices Bill Curtis ARM
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5:40 PM Wrap up / Q&A
5:45 PM Wine & Cheese Reception
6:45 PM End of Reception

Conference

Mon 8/11 Session Title Presenter Affiliation
8:15 AM Breakfast
9:15 AM Welcome Introductory Remarks
9:30 AM High Performance Computing SX-ACE Processor: NEC’s Brand-New Vector Processor Shintaro Momose NEC
SPARC64 XIfx : Fujitsu’s next generation processor for HPC Toshio Yoshida Fujitsu
Anton 2: A 2nd-Generation ASIC for molecular Dynamics Simulation J. Adam Butts and David E. Shaw D.E. Shaw Research
11:00 AM Break

11:30 AM Keynote Power Constraints: From Sensors to Servers Mike Muller ARM

12:30 PM Lunch
1:30 PM Mobile Processors NVIDIA’s Tegra K1 System-on-Chip Michael Ditty, John Montrym and Craig Wittenbrink NVidia
Applying AMD’s “Kaveri” APU for Heterogeneous Computing Dan Bouvier, Ben Sander AMD
NVIDIA’s Denver Processor Darrell Boggs, Gary Brown, Bill Rozas, Nathan Tuck and K S Venkatraman Nvidia

3:00 PM Break
3:30 PM Technology HBM: Memory Solution for Bandwidth-Hungry Processors Joonyoung Kim and Kevin Tran SK Hynix Inc
Improved 3D chip stacking with ThruChip wireless connections Dave Ditzel, Tadahiro Kuroda and Stephen Lee ThruChip Communications
CMOS Biochips for Point-of-Care Molecular Diagnostics Arjang Hassibi InSilixa

5:00 PM Break
5:30 PM ARM Servers The AMD Opteron “Seattle”: A 64b ARM Dense Server Processor Sean White AMD
ARM Next-Generation IP Supporting LSI’s High-End Networking Mike Filippo, Jamshed Jalal, Mark Werkheiser, Ann Chin, David Sonnier, Kent Fisher and Jeff Connell ARM, LSI Logic
X-Gene2: 28nm scale-out processor Gaurav Singh Applied Micro

7:00 PM Reception
Tue 8/12 Session Title Presenter Affiliation
7:00 AM Breakfast
8:00 AM FPGAs Design of a High-Density SOC-FPGA at 20nm Brad Vest, Sean Atsatt and Mike Hutton Altera
Large-Scale Reconfigurable Computing in a Microsoft Datacenter Andrew Putnam, Adrian Caulfield, Eric Chung et al Microsoft
Xilinx FPGAs case study: High capacity and Performance 20nm FPGAs Steve Young, Dinesh Gaitonde and Trevor Bauer Xilinx
SDA: Software-Defined Accelerator for Large-Scale DNN Systems Jian Ouyang, Shiding Lin, Wei Qi, Yong Wang, Bo Yu and Song Jiang Baidu

10:00 AM Break
10:20 AM High Performance ASICs Hardware-Accelerated Text Analytics Raphael Polig, Kubilay Atasu, Christoph Hagleitner et al IBM
Myriad2 “Eye” of the Computational-Vision Storm David Moloney, Brendan Barry, Richard Richmond et al Movidius
Goldstrike 1: A 1st Generation Cryptocurrency Processor for Bitcoin Mining Jim O’Connor, Timo Hanke, Javed Barkatullah and Ricky Lewelling Cointerra
RayChip: Real-time Ray Tracing Chip for Embedded Applications Woo-Chan Park, Hee-Jin Shin, Byoungok Lee et al Siliconarts

12:20 PM Lunch
1:20 PM Keynote The Internet of Everything: What is it? What’s driving it? What comes next? Rob Chandhok Qualcomm
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2:20 PM Break
2:40 PM Dense Servers and Server Technology SCORPIO: 36-Core Shared-Memory Processor with a Coherent Mesh Chia-Hsin Owen Chen, Sunghyun Park, Suvinay Subramanian MIT
Oracle’s Next Generation SPARC Cache Hierarchy Ram Sivaramakrishnan, Sumti Jairath Oracle
Unchaining the data center with Open Power: Reengineering a server ecosystem Michael Gschwind IBM
Intel C2000 Atom Microserver: Power Efficient Processing for the Data Center Brad Burres, Johan Van de Groenendaal, Jonathan Robinson et al Intel

4:40 PM Break
5:00 PM Big Iron Server Performance Characteristics of the POWER8 Processor Alex Mericas IBM
Next Generation Oracle SPARC Processor Stephen Phillips Oracle
IvyBridge Server: Delivering Performance from Workstations to Mission Critical Irma Esmer and Scott Murray Intel


Posters (** = Awarded Best Poster of Conference)

Title Presenter
Memory Processing Units ** Jaikrishnan Menon, Lorenzo De Carli, VijayraghavanThiruvengadam Karthikeyan Sankaralingam and Cristian Estan* UW-Madison and *Google
Precision Refinement for Media-Processor SoCs: fp32! fp64 on Myriad Tomasz Szydzik, University of Las Palmas of Gran Canaria, David Moloney, Movidius
Level-3 BLAS on Myriad Multi-Core Media-Processor Tomasz Szydzik, University of Las Palmas of Gran Canaria, Marius Farcas, Valeriu Ohan, Codecart, David Moloney, Movidius
Bridge Chip Composing a PCIe Switch over Ethernet to Make a Seamless Disaggregated Computer in Data-Center Scale Takashi Yoshikawa, Jun Suzuki, Green Platform Research Lab, Yoichi Hidaka, Junichi Higuchi, System Device Division, and Shinji Abe, IT Platform Division, NEC
Low Power Fixed-Latency DSP Accelerator with Autonomous Minimum Energy Tracking (AMET) Chung-Hsun Huang1,3, Wei-Jen Chen1,3, Keng-Jui Chang1,3, Yi-Hsun Ting2,3, Keng-Chang Hsu1,3, Yu-Fu Pan1,3, Chao-Chun Chen1,3, Yuan-Hua Chu4, Tay-Jyi Lin2,3, and Jinn-Shyan Wang1,3 1Department of Electrical Engineering, National Chung Cheng University (CCU), Taiwan, 2Deptartment of Computer Science and Information Engineering, CCU, Taiwan, 3SoC/AIM-HI Centers, CCU, Taiwan 4Information and Communications Research Laboratories (ICL), Industrial Technology Research Institute (ITRI), Taiwan
A Perpetuum Mobile 32bit CPU on 65nm SOTB CMOS Technology with Reverse-Body-Bias Assisted Sleep Mode Shiro Kamohara1, Nobuyuki Sugii1, Koichiro Ishibashi2, Kimiyoshi Usami3, Hideharu Amano4, Kazutoshi Kobayashi5, and Cong-Kha Pham2, 1Low-power Electronics Association & Project (LEAP), Tsukuba, Japan, 2The University of Electro-Communications, Tokyo, Japan, 3Shibaura Institute of Technology, Tokyo, Japan, 4Keio University, Yokohama, Japan, 5Kyoto Institute of Technology, Kyoto, Japan
Have Your Cake In Parallel And Eat It Sequen6ally Too! Gagan Gupta, University of Wisconsin
High-level Synthesis of Memory Bound and Irregular Parallel Applications with Bambu Vito Giovanni Castellana and Antonino Tumeo from Pacific Northwest National Laboratory, Richland, WA, USA; Fabrizio Ferrandi from Politecnico di Milano, DEIB – Milano, Italy