HC01 (1989)

Date June 26-27, 1989
Place Kresge Auditorium, Stanford University
Program Final Program PDF
Committees Organizing and Program Committees

Conference Day One

Session Monday, June 26, 1989
Opening Remarks
08:45-09:00
General Chair: Robert G. Stewart PDF
Session 1
09:00-10:45
New SPARC CPUs 
Chair: Dave Ditzel, Sun Microsystems
Cypress SPARC Program Overview, Raju Vegesna (Ross Technology) PDF

ECL SPARC Chip Set, Anant Agrawal (Sun Microsystems/Bipolar Integrated Technology) PDF

The Architecture of the P1 – A 250MHz SPARC in GaAs, Pete Wilson (Prisma) PDF

Session 2
11:00-12:30
RISC CPU Updates 
Chair: Forest Baskett, Silicon Graphics
Fujitsu SPARC Chip Set Update, Rolando Carreras (Fujitsu Microelectronics)

L64815 MCT Overview, Douglas Grundman (LSI Logic)

88K Family Update, Mitch Alsup (Motorola)

MIPS RISC Architecture, John Mashey (MIPS Computer) PDF

Clipper Update, Harlan McGhan (Intergraph)

Keynote 1
13:30-14:15
Bumps on the Path to Floating Point Progress
Invited Speaker:
 Professor W. Kahan, University of California, Berkeley PDF
Session 4 
14:30-15:30
New Processor Architecture 
Chair: Jack Grimes, MASS MicrosystemsIntel I860 Million Transistor 64-bit Microprocessor, Les Kohn (Intel)
Session 5 
15:00-16:30
Floating Point Processors 
Chair: Dave Goldberg, Xerox CorporationABACUS 3170/3171 Single Chip FP Coprocessor for SPARC, Allen Samuels, Mark Birman (Weitek)

The TMS390C602 SPARC FPU, Merrick Darley (Texas Instruments)

L64814: LSI Logic’s SPARC Floating Point Coprocessor, Peng Ang (LSI Logic)

The MIPS R3010 FPU, Earl Killian (MIPS Computer)

Conference Day Two

Session Tuesday, June 27, 1989
Session 6 
08:45-10:30
New CISC CPUs 
Chair: Mark Horowitz, Stanford University

Motorola 68040 Introduction, Motorola Semiconductor

Intel’s I486 Processor Architecture, John Crawford (Intel) PDF

Pipeline Control for a Single-Cycle VLSI Implementation of a Complex Instruction Set Computer, David R. Stiles, Harold L. McFarland (NextGen)

Session 7 
10:45-12:30
Embedded CPUs 
Chair: John Wakerly, Stanford UniversityIntel’s 960 RISC Family, Steve McGeady (Intel)

Meeting the Embedded Challenge: National’s NS32GX32, The New Generation, Jonathan Levy (National Semiconductor) PDF

AMD 29000 Update, Brett Stewart (AMD)

Session 8 
13:30-15:00
Graphics Coprocessors 
Chair: Jack Grimes, MASS Microsystems

The TMS34020 Graphics System Processor and the TMS34082 Floating Point Co-Processor, Mike Asal (Texas Instruments) 

Sun GX Graphics Workstations, The Standard for Graphics Performance from the Desktop to Powerful Deskside Systems, Curtis Priem (Sun) PDF

Panel Session 
15:30-17:00
Compiler Issues with HOT Chips 
Chair: John Mashey, MIPS ComputerPresenters:
Tom Pennello (MetaWare)
Steve Johnson (Ardent Computer)
Steve Glanville (Silicon Valley Software Trio)
Michael Tiemann (Stanford University)