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HOT CHIPS 16 Archives (2004)

General Information

HOT CHIPS 16 (2004)
Date	August 22-24, 2004
Place	Memorial Auditorium, Stanford University
Committees	Organizing and Program Committees

Tutorials

Tutorials	Sunday, August 22, 2004
Morning Tutorial 08:30-12:00	Ultrawideband; Technology and Issues Chair: Tom Petersen (MIPS Technologies) Speakers: Roberto Aiello (Staccato Communications), Anuj Batra (Texas Instruments), Nathan Belk (Texas Instruments), Sandeep Kumar (Adimos) Speaker Biographies
Afternoon Tutorial 13:30-17:00	Performance Comparison of State-of-the-Art Volatile and Non-Volatile Memory Devices Chair: Christos Kozyrakis, Stanford University Speakers: J. Thomas Pawlowski (Micron Technology)

Conference Day One

Session	Monday, August 23, 2004
Opening Remarks 9:00-9:10	Robert H Lashley, General Chair William Dally, Program Co-Chair John Mashey, Computer History Museum
Session 1 9:10-10:40	Mobile Processing Chair: Norm Jouppi (HP) Intel(R) PXA27x Processor Family: An Applications Processor for Phone and PDA Applications, Nigel Paver (Intel) SC10: A Video Processor and Pixel Shading GPU For Handheld Devices, Edward Hutchins (NVIDIA) SH-Mobile3: Application Processor for 3G Cellular Phones on a Low-Power SoC Design Platform, Hiroyuki Mizuno, N.Irie, K.Uchiyama (Hitachi), Y. Yanagisawa, S. Yoshioka, I. Kawasaki (Renesas Technology Corp.), T. Hattori (SuperH Japan Ltd.)
Keynote 1 11:00-12:00	Mars Exploration Rovers -- a View from the Inside, Robert Denise (JPL)
Session 2 12:00-1:00	Wireless Communication Chair: Mitsuo Saito (Toshiba) IEEE802.11a Based Wireless AV Module (WAVM), Takashi Wakutsu, N.Shibuya, E.Kamagata, T.Matsumoto, Y.Nagahori, T.Sakamoto, Y.Unekawa, K.Tagami, M.Serizawa (Toshiba) Single Chip CMOS Direct Conversion Transceivers for WWAN and WLAN, Tajinder "Taj" Manku (Sirific Wireless)
Session 3 2:00-3:00	Media and Graphics Processing Chair: John Nickolls (NVIDIA) NVIDIA GeForce 6800, John Montrym, Henry Moreton (NVIDIA) Architecture of the Intel(R) MXP5800 Digital Media Processor, Lou Lippincott, Arup Gupta, Glenda Dorchak (Intel)
Session 4 3:30-4:30	Enabling Technology Chair: John Sell (AMD) SimNow™: Fast Platform Simulation Purely In Software, Robert Bedichek (AMD) Active Micro-Channel Cooling, Andy Keane (Cooligy)
Session 5 4:30-5:30	System Components Chair: John Sell (AMD) The RM9150 and the Fast Device Bus High Speed Interconnect, John R. Kinsel (PMC-Sierra) HORUS - Enabling large scale, 32-way Opteron Enterprise Servers, Rich Oehler and Rajesh Kota (Newisys)
Panel Discussion 6:45-9:30	Outsourcing Engineering Development Offshore Moderator: John Nickolls (nVidia) T.J. Rodgers (Cypress Semiconductor), Vinod Dham (NewPath Ventures), Natasha Humphries (TechsUnite), Ron Hira (IEEE-USA, Rochester Inst. Technology), Carl Everett (Accel Partners), Pratul Shroff (eInfoChips) Panelist Biographies

Conference Day Two

Session	Tuesday, August 24, 2004
Session 6 8:40-10:10	Potpourri Chair: Christos Kozyrakis (Stanford University) MDGRAPE-3 chip: A 165-Gflops application-specific LSI for molecular dynamics simulations, Makoto Taiji (RIKEN) Accelerating Next-Generation Public-key Cryptography on General-Purpose CPUs, Hans Eberle, Sheueling Chang Shantz, Vipul Gupta, Nils Gura (Sun) How SolarFlare Communications broke the 10Gbps on UTP barrier, Ron Cates (SolarFlare)
Keynote 2 10:30-11:30	Nanotech and the Future of Moore's Law Steve Jurvetson (Draper Fisher Jurvetson)
Session 7 11:30-12:30	Embedded Systems Chair: Tom Petersen (MIPS Technologies) A Fast Powertrain Microcontroller, Erik Norden, Patrick Leteinturier, Jens Barrenscheen, Klaus Scheibert, Frank Hellwig (Infineon) The Mote Revolution: Low Power Wireless Sensor Network Devices, Joseph Polastre, Robert Szewczyk, Cory Sharp, David Culler (UC Berkeley)
Session 8 1:30-2:30	Low-Power Processors Chair: Forest Baskett (NEA) A 90nm embedded DRAM single chip LSI with a 3D graphics, H.264 codec engine, and a reconfigurable processor, Masanobu Okabe (Sony) Low Power AMD Athlon™64 and AMD Opteron™ Processors, Marius Evers (AMD)
Session 9 2:50-4:20	Instruction Set Automation Chair: Chris Rowen (Tensilica) The End of ISA Design: Power Tools for Optimal Processor Generation, David Goodwin (Tensilica) Long Words and Wide Ports: Reinventing the Configurable Processor, Dhanendra Jani, Gulbin Ezer, James Kim (Tensilica) OptimoDE: Programmable Accelerator Engines Through Retargetable Customization, Scott Mahlke, Nathan Clark, Hongtao Zhong, Kevin Fan (University of Michigan), Krisztian Flautner, Koen Van Nieuwenhove (ARM)
Session 10 4:50-6:20	High-End Processors Chair: Pradeep Dubey (Intel) Montecito - The next product in the Itanium(R) Processor Family, Cameron McNairy (Intel), Rohit Bhatia (HP) A 32-way Multithreaded SPARC(R) Processor, Poonacha Kongetira (Sun) Intel Pentium(R) 4 Processor(R) on 90nm Technology, Ronak Singhal (Intel)

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