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• Part 1: Virtual Machines - Architectures, Implementations, and Applications
  James E. Smith (Professor, University of Wisconsin at Madison, ECE)
  
• Part 2: Virtual Machines - System Virtual Machines
  Richard Uhlig (Senior Staff Member, Intel, MRL, Oregon)

• Part 1: Power efficiency in CMOS VLSI Circuits
  Kevin Nowka (IBM Austin Research Laboratory)
  
• Part 2: Power-aware Microarchitectures: Design, Modeling and Metrics
  Pradip Bose (IBM T.J. Watson Research Center)
  
• Part 3: Designing for Power: Tools and Methodology
  Sani Nassif (IBM Austin Research Laboratory)
  

• General Chair: Pradeep K. Dubey (Intel)
• Program Chairs: Alan Smith (University of California, Berkeley), John Sell (Microsoft)
• Computer History Museum: John Mashey

A novel SIMD architecture for the Cell heterogeneous chip-multiprocessor
Michael Gschwind, Peter Hofstee, Brian Flachs, Marty Hopkins, Yukio Watanabe, Takeshi Yamazaki (IBM)

Cell Broadband Engine Interconnect and Memory Interface
Scott Clark, Kent Haselhorst, Kerry Imming, John Irish, Dave Krolak, Tolga Ozguner (IBM)

Super Companion Chip with Audio Visual Interface for Cell Processor
Takayuki Mihara, Kenichi Ishii, Naoki Sugawa (Toshiba)

Programming and Performance Evaluation of the CELL Processor
Ryuji Sakai, Seiji Maeda, Christopher Crookes, Mitsuru Shimbayashi, Katsuhisa Yano, Tadashi Nakatani, Hirokuni Yano, Shigehiro Asano, Masaya Kato, Hiroshi Nozue, Tatsunori Kanai, Tomofumi Shimada, Koichi Awazu (Toshiba)

A Milliflow Aggregation Processor, Bapi Vinnakota (Intel)

Barcelona: a Fibre Channel Switch SoC for Enterprise SANs, Nital P. Patwa (Cisco)

High-Performance Pattern-Matching Engine for Intrusion Detection, Jan van Lunteren, Ton Engbersen (IBM)

CMOS Photonics Technology - Enabling Optical Interconnects, Cary Gunn (Luxtera)

40-GHz Operation of a Single-flux-quantum (SFQ) Switch Scheduler, ISTEC: Y. Kameda, S. Yorozu, Y.Hashimoto (ISTEC), H. Terai (NICT), A. Fujimaki (Nagoya University), N. Yoshikawa (Yokonama National University)

Telairity-1: A Real Time H.264 High Definition Video Architecture , Richard Dickson (Telairity)

Next-Generation Audio Engine, Robert Kennedy (Tensilica)

High Speed Low Cost Nexperia PNX1700 Super-Pipelined Media-Processor, Luis Lucas (Philips)

An Ultra High Performance, Scalable DSP Family for Multimedia, Erik Machnicki (Cradle)

Moderator: Pradeep Dubey (Intel), Edward Frank (Broadcom), Ajay Luthra (Motorola), David Kirk (Nvidia), Nick Tredenick (Gilder Technology)

Panelist Biographies

Low-Power, Networked MIMD Processor for Particle Physics, Dr. Volker Lindenstruth (University of Heidelberg)

The Design and Implementation of the TRIPS Prototype Chip, Robert G. McDonald (University of Texas)

Digitally Assisted Analog Circuits, Boris Murmann (Stanford University)

A 1-Ghz Configurable Processor Core - MeP-h1, Takashi Miyamori (Toshiba)

Software Configurable Processors Change System Design , Ricardo E. Gonzalez (Stretch)

DAPDNA-2: A Dynamically Reconfigurable Processor w/376 32-bt Processing Elements , Tomoyoshi Sato (IPFlex)

Ascenium: A Continuously Reconfigurable Architecture , Robert Mykland (Ascenium)

The Nios II Family of Configurable Soft-core Processors , James Ball (Altera)

High-Performance Processing with 90-nm FPGAs , Erich Goetting, Peter Alfke, Kees Vissers (Xilinx)

The Design and Applications of BEE2: A High End Reconfigurable Computing System , Chen Chang, John Wawrzynek, Robert W. Brodersen (University of California, Berkeley)

Intel 8xx series and Paxville Xeon-MP Microprocessors, Jonathan Douglas (Intel)

TwinCastle: A Multiprocessor North Bridge Server Chipset, Debendra Das Sharma, Ashish Gupta, Gordon Kurpanek, Dean Mulla, Bob Pflederer, Ram Rajamani (Intel)

Dynamically Optimized Power Efficiency with Foxton Technology, Samuel Naffziger (Intel)

Xbox 360 System Architecture
Jeff Andrews and Nick Baker (Microsoft)