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• Approaches to System Design for the Working Engineer.
  
  
• Part I: ASICs To ASSPs For Working Engineers (Building the OMAP 3430)
  Author: David Witt, Texas Instruments
• Part II: 20 Years Of FPGA Evolution: From Glue Logic To Systems Components
  Author: Peter Alfke, Xilinx
• Part III: Exploiting Processor Heterogeneity Through Reconfigurable Interactions
  Author: Shepard Siegel, Mercury Computer Systems

• Enterprise Power and Cooling: A Chip-to-Data Center Perspective.
  
  Part I: Background
  Part II: Cooling: A Chip-Core to Cooling-Tower Perspective
  Part III: Power: From Chips to Data Centers
  Part IV: Case Study and Future Directions
  Author(s): Chandrakant Patel and Parthasarathy Ranganathan, HP Labs
  
  

• Fault-Tolerant Design of the IBM POWER6™ Microprocessor.
Authors(s): Kevin Reick, Pia N. Sanda, Scott Swaney, Jeffrey W. Kellington, Michael Floyd (IBM)

• System Performance Scaling of IBM POWER6™ Based Servers.
Authors(s): Jeff Stuechell (IBM)

• The 3rd Generation of IBM's Elastic Interface (EI-3) Implementation of POWER6™.
Authors(s): Daniel Dreps (IBM)

• NVIDIA GeForce 8800™ GPU.
Author(s): Erik Lindholm, Stuart Oberman (NVIDIA)

• NVIDIA GPU Parallel Computing Architecture.
Author(s): John Nickolls (NVIDIA)

• Performance of Non-Graphics Applications on the GeForce 8800™and the CUDA™ Parallel-Programming Environment.
Author(s): Wen-Mei Hwu (UIUC), David Kirk (NVIDIA), Shane Ryoo (UIUC), John A. Stratton (UIUC), Kuangwei Hwang (UIUC)

• Radeon R600, a 2nd Generation Unified Shader Architecture.
Author(s): Michael Mantor (AMD)

• Teraflop Prototype Processor with 80 Cores.
Author(s): Yatin Hoskote, Sriram Vangal, Nitin Borkar, Shekhar Borkar (Intel)

• Design and Implementation of the TRIPS Prototype Chip.
Author(s): Madhu Sravana Sibi Govindan, Doug Burger, Steve Keckler (U Texas Austin)

• Tile Processor: Embedded Multicore for Networking and Multimedia.
Author(s): Anant Agarwal, Liewei Bao, John Brown, Bruce Edwards, Matt Mattina, Chyi-Chang Miao, Carl Ramey, David Wentzlaff (Tilera Corporation)

• SH-X3: SuperH Multi-Core for Embedded Systems.
Author(s): Shinichi Shibahara (Renesas), Masashi Takada (Hitachi), Tatsuya Kamei, Kiyoshi Hayase, Yutaka Yoshida, Osamu Nishii, Toshihiro Hattori (Renesas)

• An HD Image Processor for Low-Cost Entertainment Products.
Author(s): Deepu Talla (Texas Instruments)

• A Professional H.264/AVC CODEC Chip-Set for HDTV Broadcast Infrastructure and High-End Flexible CODEC Systems.
Author(s): Mitsuo Ikeda, Hiroe Iwasaki, Koyo Nitta, Takayuki Onishi, Takeshi Sano, Atsushi Sagata, Yasuyuki Nakajima, Minoru Inamori, Takeshi Yoshitome, Hiroaki Matsuda, Ryuishi Tanida, Atsushi Shimizu,Jiro Naganuma (NTT)

What's Next After CMOS?
Moderator: Norm Jouppi, Hewlett Packard

Panelists:
John Kubiatowicz (UC Berkeley)
Mike Mayberry (Intel)
Mark Horowitz (Stanford University)
Stan Williams (Hewlett Packard)
Ghavam Shahidi (IBM)

• Multi-terabit Switch Fabrics Enabled by Proximity Communication.
Author(s): Hans Eberle (Sun)

• Thyristor RAM: A High-Speed High-Density Embedded Memory.
Author(s): Farid Nemati (T-RAM Semiconductor)

• Raksha: A Flexible Architecture for Software Security.
Author(s): Hari Kannan, Michael Dalton, Christos Kozyrakis (Stanford University)

• A 4Gbps Wireless Uncompressed 1080p 60 GHz HD Transceiver.
Author(s): Jeff Gilbert (SiBEAM)

• A 2x2 MIMO Baseband for Wireless Local-Area Network (802.11n).
Author(s): Jason A. Trachewsky (Broadcom)

• Chesapeake: A 50Gbps Network Processor and Traffic Manager.
Author(s): Brian Alleyne (Bay Microsystems)

• A System-on-a-Chip with Integrated Accelerators.
Author(s): Rumi Zahir (Intel)

• Focalpoint II, A Low-Latency, High Bandwidth Switch/Router Chip.
Author(s): Uri Cummings, Mike Zeile (Fulcrum Microsystems)

• Power Management Features in Penryn 45nm Core2™ Duo.
Author(s): Varghese George (Intel)

• Next Generation Mobile x86 Processor.
Author(s): Jonathan Owen (AMD)

• nForce 680i and 680 Platform Processors.
Author(s): Brian Langendorf (NVIDIA)

• VictoriaFalls - Scaling Highly-Threaded Processor Cores.
Author(s): Stephen Phillips (Sun)

• The Next-Generation Mainframe Microprocessor.
Author(s): Charles Webb (IBM)