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HOT CHIPS 4 Archives (1992)

General Information

HOT CHIPS 4 (1992)
Date	August 9-11, 1992
Place	Memorial Auditorium, Stanford University
Program	Final Program
Committees	Organizing and Program Committees

Tutorials

Tutorials	Sunday, August 9, 1992
Morning Tutorial 11:00-13:00	A Quantitative Approach to Microprocessor Architecture (Part 1) Chair: Professor Mark D. Hill
Afternoon Tutorial 13:30-15:30	A Quantitative Approach to Microprocessor Architecture (Part 2) Chair: Professor Mark D. Hill

Conference Day One

Session	Monday, August 10, 1992
Opening Remarks 08:45-09:00	General Chair: Glen Langdon Program Co-Chairs: David Patterson, John Mashey
Session 1 09:00-10:15	High Performance Processors (Part 1) Chair: David Patterson, University of California, Berkeley DEC Alpha Architecture and 21064 Chip, E. McLellan (Digital Equipment Corporation) A 200 MFLOP HP PA-RISC Processor, W. Jaffe, B. Miller, J. Yetter (Hewlett-Packard)
Session 2 10:45-12:15	Multiprocessor Interface Issues Chair: Ruby Lee, Hewlett-Packard Multiprocessor Features in a PA-RISC Processor Interface Chip, T. Alexander, K. Chan, C. Hu, N. Noordeen, S. Ziai (Hewlett-Packard) On-Chip Cache Hierarchy for 1000-MIPS Multi-Superscalar Processors, T. Nishimukai, M. Hanawa, O. Nishii, M. Suzuki, K. Yano, M. Hiraki (Hitatchi) Sparcle: Today's Micro for Tomorrow's Multiprocessor, A. Argarwal (MIT)
Session 3 13:45-15:15	Low Cost Processors Chair: John Mashey, Silicon Graphics Highly Integrated SPARC Processor Implementation, S. Joshi (Sun Microsystems) The LR33020 GraphX Processor: A Single Chip MIPS-RISC Based X Terminal Controller, S. Desai (LSI Logic) The ARM600 Processor and FPA, M. Muller (Advanced RISC Machines)
Session 4 15:45-17:15	Low Power Systems Chair: Dave Ditzel, Sun Microsystems A VLSI Chip Set for Personal Communications Systems, R. Scauzzo (AT&T Bell Labs) SPARC90 – Chipset on a Chip, J. Pendleton (Sun Microsystems) Cold Chip Design Techniques, R. Broderson, A. Chandrakasan, S. Sheng (University of California, Berkeley)
Panel Discussion 19:15-21:30	DRAM Choices for the '90s: 1 Gigabyte/Second or Bust Moderator: Skip Stritter, Silicon Graphics Panelists: Rambus – M. Horowitz (Stanford) Ramlink – D. James (Apple Computer) Synchronous DRAM – W. Vokley (Texas Instruments) Cache DRAM – C. Hart (Mitsubishi)

Conference Day Two

Session	Tuesday, August 11, 1992
Session 5 09:00-10:30	Interfaces and Interrupts Chair: John Mashey, Silicon Graphics The SBus Goldchip, M. Sodos (Sun Microsystems) Peripheral Component Interconnect, D. Carson (Intel) Advanced Programmable Interrupt Controller (APIC) for MP and 32-bit Operating Systems, P.K. Nizar (Intel)
Session 6 11:00-12:30	Vector and Video Chair: Dave Patterson, University of California, Berkeley The Vector Coprocessor (VU) for the CM-5, J. Wade (Thinking Machines Corp) A 289 MFLOPS Single Chip Supercomputer, C. Lund for H. Lino, H. Takahashi, T. Sukemura, M. Kimura, K. Fukita, S. Mori (Fujitsu) A Programmable Solution for Standard Video Compression, J. Fandrianto, T. Williams (Integrated Information Technology)
Session 7 14:00-15:30	Electrons, Photons, and Neurons Chair: Teresa Meng, Stanford University Chip Pair Creates Self-Timed Network Fabirc for Paragon Parallel Supercomputers, R. Traylor, D. Dunning (Intel Supercomputer Systems) GaAs VLSI Enhancement through Utilization of Global Optical Free Space 'Smart' Interconnects, P. Guifoyle, F. Zeise (OptiComp Corp) Silicon Based Nerve Interfaces, G. Kovacs (Stanford University)
Session 8 16:00-17:00	High Performance Processors (Part 2) Chair: Uri Weiser, Intel The Second Generation SPARCore Mbus Chip, M. Guiterrez (Ross Technology) Superscalar Architecture of the P5 - X86 Next Generation Microprocessor, D. Alpert (Intel) The P5 Floating-Point Unit, D. Avnon (Intel)

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