HOT CHIPS 9 Archives (1997)
General Information
| HOT CHIPS 9 (1997) |
| Date |
August 24-26, 1997 |
| Place |
Kresge Auditorium, Stanford University |
| Program |
Final Program  |
| Committees |
Not Available |
Tutorials
| Tutorials |
Sunday, August 24, 1997 |
Morning Tutorial
08:30-12:00 |
Sorting Out the New DRAMs
Chair: Steven Przybylski, Verdande Group, Inc.
|
Afternoon Tutorial
13:00-17:00 |
Architecture and Design Implications of Mediaprocessing
Chair: Pradeep Dubey, IBM T.J. Watson Research Center
|
Conference Day One
| Session |
Monday, August 25, 1997 |
Opening Remarks
09:00-09:15 |
General Chair: S. Diane Smith
Program Co-Chairs: Allen J. Baum, Alan Jay Smith |
Session 1
09:15-10:45
|
Research Machines
Chair: John Wawrzynek, University of California, Berkeley
The MIT Multi-ALU Processor, Steve Keckler (MIT Artificial Intelligence Laboratory) 
MATRIX: A Reconfigurable Computing Device with Configurable Instruction Distrobution, Eathan Mirsky (MIT Artificial Intelligence Laboratory) 
TITAC-2: A 32-bit Scalable-Delay-Insensitive Microprocessor, Takashi Nanya (University of Tokyo) 
|
Session 2
11:15-12:45
|
Specialized Chips
Chair: Mitsuo Saito, Toshiba
Intel 82440LX PCI Chipset, Richard Malinowski (Intel) 
1/4 Inch CMOS Active Pixel Sensor with Smart On-Chip Functions and Full Digital Interface, E.R. Fossum (Photobit) 
The VelociTI™ Architecture of the TMS320C6x, Loc Truong (Texas Instruments)  |
Keynote 1
14:00-14:45 |
Gigascale Integration: Is the Sky the Limit?
Chair: Robert Garner, Sun Microsystems
Speaker: James Meindl |
Session 4
14:45-15:45
|
Virtual Machines
Chair: Monica Lam, Stanford University
The Design of the Inferno Machine, Phil Winterbottom, Rob Pike (Bell Labs) 
Digital FX!32: A Utility for Fast Transparent Execution of Win32 x86 Applications on Alpha NT, Norm Rubin (Digital Equipment Corp) 
Java on Steroids: Sun's High-Performance Java Implementation, Urs Heitzle (Javasoft, University of California, Santa Barbara)  |
Session 5
16:15-17:45
|
Performance Analysis
Chair: Forest Baskett, Silicon Graphics, Inc.
Effectiveness of the MAX-2 Multimedia Extensions for PA-RISC 2.0 Processors, Ruby Lee (Hewlett-Packard) 
Continuous Profiling (It's 10:43; Do you know Where Your Cycles Are?), Jennifer Anderson (Digital Equipment Corp) 
|
Panel Discussion
19:30-21:30
|
If **I** Were Defining 'Merced'
Moderators: John H. Wharton, Applications Research |
Conference Day Two
| Session |
Tuesday, August 26, 1997 |
Session 7
09:00-10:30
|
Embedded Processors
Chair: Allen J. Baum, Digital Equipment Corporation
SH4 RISC Microprocessor for Multimedia, Fumio Arakawa (Hitachi Central Research Labs) 
Embedded Multimedia Superscalar RISC Processor with Rambus Interface, Tomohisa Arai (NEC) 
The StrongARM SA-1100 - A Portable Communications Microprocessor, Jeff Slaton (Digital Equipment Corp) 
|
Session 8
11:00-12:30
|
Media/3D/Graphics Processors (Part 1)
Chair: Paul Kalapathy, Chromatic
Overview of the Laguna II Rambus Multimedia Accelerator, Mike Buchanan (Cirrus Logic)
A Programmable Video Coprocessor, Dominique Barthel (France Telcom) 
R3D/100 - 3D High Performance Chipset, Jeff Potter (Real3D)
Efficient High Performance 3D Pipeline Implementation on a Media Processor, Jim Battle (Chromatic) |
Keynote 2
14:00-15:30 |
HDTV and Other Advances in Communications and Broadcasting
Chair: Alan Jay Smith, University of California, Berkeley
Speaker: Reed Hundt, Chairman, Federal Communications Commission |
Session 10
16:00-17:00
|
Media/3D/Graphics Processors (Part 2)
Chair: Keith Diefendorff, Apple Computer, Inc.
Glint Gamma: A 3D Geometry and Lighting Processor for the PC, Neil Trevett (3Dlabs) 
Reality Co-Processor, Ken Hayes (Silicon Graphics, Inc.) 
Pyramid3D Real-time Graphics Processor, Kok Chin Chang (TriTech Microelectronics International)  |
Session 11
17:00-18:30
|
High-End CPUs
Chair: Dileep Bhandarkar, Intel
A 250MHz 5W PowerPC Microprocessor with On-Chip L2 Cache Controller, Brad Burgess (Motorola)
UltraSparc™ IIi - A Highly Integrated 300 MHz 64-bit SPARC V9 CPU, Kevin Normoyle (Sun Microsystems) 
The PentiumAE II CPU: A High Performance Dynamic Execution Processor with MMX™ Technolgoy, Nimish Modi (Intel)
|