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A major enabler of Moore's
Law is the rapid scaling of IC design rules, which have been reduced by
factor of - 0.7 every two or three years. The IC industry is committed
to maintaining Moore's Law as long as possible, continuing the scaling
at the historical rate. The 2001 International Technology for Semiconductors
has projected design rules through 2016 with that assumption. An important
finding is that because certain key limits are being approached, there
will be increasing difficulties over this period in maintaining this technology
scaling rate.
In this tutorial, three major areas of IC technology are addressed. MOSFET
devices and front-end process integration, interconnect, and lithography.
For each area, the scaling projections are discussed, key issues and challenges
are assessed, and potential solutions for the challenges are evaluated,
all through the year 2016.
• MOSFET and front-end process integration: classical planar
bulk CMOS technology limits and when those limits are likely to be reached,
possiblities for non-classical devices (i.g. ultra-thin body SOI or double-gate
MOSFETs) to enable continued scaling, and front-end process solutions (e.g.
high-k gate dielectrics, metal electrodes, raised source/drains, etc) are
all discussed.
• Interconnects: key issues and limits of advanced copper metal
lines scaling and low-k dielectrics, discussion of approaches such as optical
interconnect that can potentially extend beyond these limits.
• Lithography: limits and important issues of optical scaling
techniques from 248 nm-> 193 nm->157 nm exposure systems, prospects
for Extreme-UV (EUV) lithography, employing the soft X-ray wavelength of
13.4 nm. EUV is widely seen as the successor of 157-nm excimer-laser-based
lithography to extend photon-based lithography down to at least the 32
nm generation of semiconductor manufacturing.
(MOSFETS)
Peter M. Zeitzoff, Senior Fellow, International SEMATECH
(LITHOGRAPHY)
Dr. Alfred K. Wong , Assoc. Prof., Dept. of Elec. & Electronic Eng , Univ. of Hong Kong
(INTERCONNECTS)
Dr. Michael E. Thomas, Sr. Technology Fellow, Honeywell Electronic Materials Div
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