HOT CHIPS 16 Final Program

This tutorial delves into the major issues surrounding the emerging UWB environment. We discuss some of the fundamental technology issues of this PHY in both the analog and digital domains. This topic is elaborated using real world designs to consider the key system level issues that manifest in UWB based designs. We follow the technology discussions with target market descriptions and explore the opportunities that UWB technologies enable. Our discussions are hosted by the drivers behind UWB, system architects and chip implementers. They describe and discuss the tradeoffs that they faced during their development of the UWB specs and the initial implementations.

Biographies

Dr. Aiello is founder and CEO of Staccato Communications, Inc. He is a recognized leader in the ultrawideband (UWB) community and is actively involved in standardssetting committees. Dr. Aiello is a founding member of both the IEEE 802.15.3a and the 802.15.4a Groups and of the Multiband OFDM Alliance.

Dr. Aiello holds a Ph.D. degree in physics from the University of Trieste. He has authored more than 20 patents on UWB technology.

Anuj Batra is currently a Member, Group Technical Staff at TI and his research interests are in the areas of wireless communications, in particular, the design of high-speed wireless networks, multi-user detection theory, and coexistence between unlicensed wireless devices. Since joining TI, he has also been involved in standardization activities for MBOA SIG, IEEE 802.15.3a, IEEE 802.11g, IEEE 802.15.2 and Bluetooth SIG.

Dr. Batra received the B.S. degree, with distinction, in electrical engineering from Cornell University, Ithaca, NY, in 1992; the M.S. degree in electrical engineering from Stanford University, Stanford, CA, in 1993; and the Ph.D. degree in electrical engineering from Georgia Institute of Technology, Atlanta, in 2000.

Nathan Belk is the Lead RF architect within the DSPS R&D center at Texas instruments. He is a developer of the systems specification and the lead designer for TI’s MBOA UWB RFIC. Prior to this he was a Distinguished Member of Technical Staff in the Wireless Research Laboratory at Bell Labs Basic Research where he developed radio architectures, RF circuit solutions, integrated RF components and modeling algorithms.

Nathan received his BS from the University of Minnesota and his PhD from MIT.

Mr. Sandeep Kumar is co-Founder, President and CEO of Adimos Inc a fabless semiconductor startup developing and marketing innovative wireless multimedia home networking solutions. He has helped build a company that has achieved significant business successes in its very 1st year and raise 16M$ of capital.

Mr. Kumar holds an MSEE from University of Cincinnati & a BSEE from IIT Delhi, India.

Between vendor vested interests, presentation hype and datasheet specsmanship, it is often difficult to determine which memory devices are truly the most appropriate for an application in question. This is true for both volatile (DRAM, SRAM and pseudo-SRAM) and non-volatile (NOR and NAND FLASH) memory devices. This 3 hour tutorial will objectively examine the memories available today and in the reasonably near future, including SRAMs such as QDR II, DDR II and QDR III; DRAMs such as DDR2, GDDR3, FCRAM, RLDRAM and XDR, low-power volatile memory devices such as LPDRAM and PSRAM, and low-power non-volatile memory devices such as NOR and NAND FLASH. A brief description will be made concerning external operation of the major devices and where necessary some description of internal operation. The devices will be compared by performance (usable bandwidth under various operating scenarios, energy usage under these scenarios and signal count). Example operating scenarios include random operations, streaming requests with defined read/write ratios and resource predictability, streaming requests with defined read/write ratios but no predictable resource availability, etc. Performance comparisons are made using a cycle-accurate memory comparison software tool written by the author and empirically verified. Cost factors will be considered, including silicon area and test cost of competing architectures. A brief attempt will be made to assess market size and dynamics of the major devices where possible. Conclusions will be drawn for each major operating scenario concerning performance/cost ratios. Wherever possible, practical application examples will be illustrated to make the operating scenarios relevant to the system design tasks faced today and in the reasonably near future.

Bio: As Senior Director of Architecture Development in Micron's NetCom group, Thomas Pawlowski is responsible for Micron memory product definition for networking and communications applications. During his tenure at Micron, Tom has created or co-created the following devices: Reduced Latency DRAM-II, Pipelined Burst Synchronous SRAM, Zero Bus Turnaround SRAM, Double Data Rate SRAM and Quad Data Rate SRAM. Tom holds over 80 U.S. and international patents, with more pending.

Prior to joining Micron in 1992, Tom's spent eight years at Allied Signal Aerospace.  He holds a bachelor of applied science degree in electrical engineering from the University of Waterloo, Ontario, Canada.

Opening Remarks

• Intel® PXA27x Processor Family: An Applications Processor for Phone and PDA Applications, Nigel Paverl (Intel)
• SC10: A Video Processor and Pixel Shading GPU For Handheld Devices, Edward Hutchins (NVIDIA)
• SH-Mobile3: Application Processor for 3G Cellular Phones on a Low-Power SoC Design Platform, Hiroyuki Mizuno, N.Irie, K.Uchiyama (Hitachi), Y. Yanagisawa, S. Yoshioka, I. Kawasaki (Renesas Technology Corp.), T. Hattori (SuperH Japan Ltd.)

• IEEE802.11a Based Wireless AV Module (WAVM), Takashi Wakutsu, N.Shibuya, E.Kamagata, T.Matsumoto, Y.Nagahori, T.Sakamoto, Y.Unekawa, K.Tagami, M.Serizawa (Toshiba)
• Single Chip CMOS Direct Conversion Transceivers for WWAN and WLAN, Tajinder "Taj" Manku (Sirific Wireless)

• NVIDIA GeForce 6800, John Montrym, Henry Moreton (NVIDIA)
• Architecture of the Intel® MXP5800 Digital Media Processor, Lou Lippincott, Arup Gupta, Glenda Dorchak (Intel)

• SimNow™: Fast Platform Simulation Purely In Software, Robert Bedichek (AMD)
• Active Micro-Channel Cooling, Andy Keane (Cooligy)

• The RM9150 and the Fast Device Bus High Speed Interconnect, John R. Kinsel (PMC-Sierra)
• HORUS - Enabling large scale, 32-way Opteron Enterprise Servers, Jeff Gruger and Rajesh Kota (Newisys)

• MDGRAPE-3 chip: A 165-Gflops application-specific LSI for molecular dynamics simulations, Makoto Taiji (RIKEN)
• Accelerating Next-Generation Public-key Cryptography on General-Purpose CPUs, Hans Eberle, Sheueling Chang Shantz, Vipul Gupta, Nils Gura (Sun)
• How SolarFlare Communications broke the 10Gbps on UTP barrier, Ron Cates (SolarFlare)

• A Fast Powertrain Microcontroller, Erik Norden, Patrick Leteinturier, Jens Barrenscheen, Klaus Scheibert, Frank Hellwig (Infineon)
• The Mote Revolution: Low Power Wireless Sensor Network Devices, Joseph Polastre, Robert Szewczyk, Cory Sharp, David Culler (UC Berkeley)

• A 90nm embedded DRAM single chip LSI with a 3D graphics, H.264 codec engine, and a reconfigurable processor, Masanobu Okabe (Sony)
• Low Power AMD Athlon™64 and AMD Opteron™ Processors, Marius Evers (AMD)

• The End of ISA Design: Power Tools for Optimal Processor Generation, David Goodwin (Tensilica)
• Long Words and Wide Ports: Reinventing the Configurable Processor, Dhanendra Jani, Gulbin Ezer, James Kim (Tensilica)
• OptimoDE: Programmable Accelerator Engines Through Retargetable Customization, Scott Mahlke, Nathan Clark, Hongtao Zhong, Kevin Fan (University of Michigan), Krisztian Flautner, Koen Van Nieuwenhove (ARM)

• Montecito - The next product in the Itanium® Processor Family, Cameron McNairy (Intel), Rohit Bhatia (HP)
• A 32-way Multithreaded SPARC® Processor, Poonacha Kongetira (Sun)
• Intel Pentium® 4 Processor® on 90nm Technology, Ronak Singhal (Intel)