Date: Sunday, August 14, 2005
Location: Memorial Auditorium, Stanford University.

Last Updated: August 12, 2005

8:30-10:00am Breakfast
 
10:00-1:30pm Morning Tutorial

Session Chair: Christos Kozyrakis

Presentation: Virtual Machines-Architectures, Implementations, and Applications

Authors(s):

  • James E. Smith: Professor, University of Wisconsin at Madison, ECE
  • Richard Uhlig: Senior Principal Engineer, Intel Corporate Technology Group (CTG), Oregon

Abstract:

Virtual machines have emerged as a powerful tool for computer systems designers. They can be used to enhance software interoperability, mobility, and security, as well as providing means for effective hardware resource management.

We survey the spectrum of VM architectures and their applications.

These range from the HLL VMs as exemplified by Java, to process VMs that permit cross-platform execution of conventional binaries, to system VMs which support multiple OS environments on a single platform. We then look at some of the important VM architectures and discuss their implementations and features. We will emphasize architecture and hardware mechanisms that provide efficient support for VMs. Several case studies will be discussed, chosen from both commercial implementations and research project
1:30-2:30pm Lunch
2:30-6:00pm

Afternoon Tutorial

Session Chair: Christos Kozyrakis

Overall Title: Low Power, High Performance Microprocessor Design

Part 1: Power efficiency in CMOS VLSI Circuits
Authors(s): Kevin Nowka

Abstract:

This part of the tutorial will examine the circuit contributions to power consumption in VLSI designs, examine the trends in CMOS circuit designs related to power efficiency, and present techniques to limit both the active and leakage power in CMOS VLSI circuits. The concentration will be on techniques employed by commercial processor designs and consumer electronic devices.

Part 2: Power-aware Microarchitectures: Design, Modeling and Metrics
Authors(s): Pradip Bose

Abstract:

This segment of the tutorial will focus on power-awareness at the early, microarchitecture definition stage of design.

Power-performance tradeoff modeling and analysis, with a clear notion of the associated efficiency metrics is a key aspect of the design process at this stage; as such, we will start with that topic. We will then review the key new ideas in power-aware microarchitectures that are of practical interest and promise in the current era of power-constrained microprocessor design.

Part 3: Designing for Power: Tools and Methodology

Authors(s): Sani Nassif, IBM Research - Austin

Abstract:

The advent of the 100+ Watt chip threatens to derail the long standing performance gains we have been counting on from technology scaling according to Moore's law. Phenomena such as leakage and technology-induced variability further worsen this trend. This has been contributed to by a design methodology which emphasizes performance (frequency) at all costs and all but ignores power dissipation. The industry is now in desperate need for a power-oriented design methodology which treats power as a first class objective, and that allows designers to make power/performance and power/area trade-offs at the micro-architectural, circuit, and even technology levels. This talk will outline some of the requirements for such a methodology, propose some potential solutions, and focus specifically on the linkages between power and technology.

6:00-7:00pm Wine and Cheese Reception

Authors Bio

James E. Smith is a professor in the Department of Electrical and Computer Engineering at the University of Wisconsin Madison. He received his PhD in 1976 from the University of Illinois. Since then, he has been involved in a number of computer research and development projects as a faculty member at Wisconsin and in industry (Control Data Corporation, Astronautics Coporation, Cray Research). Currently, he and his research group are studying the virtual machine abstraction as a technique for providing high performance and power efficiency through co-design and tight coupling of virtual machine hardware and software.

Professor Smith recieved the ACM/IEEE 1999 Eckert-Mauchly Award for contributions to the field of computer architecture. He is co-author with Ravi Nair of a book on virtual machines recently published by Morgan-Kaufmann.

Richard Uhlig is is a Senior Principal Engineer in Intel's Corporate Technology Group, where he is currently leading efforts within Intel to bring hardware virtual-machine support to IA-based systems as part of the "Intel Virtualization Technology (VT)" program. Prior to joining Intel in 1996, Rich held a post-doctoral fellowship at the European national research labs of Germany (GMD), Greece (FORTH), and France(INRIA), where he extended his graduate-school research into hardware support for micro-kernel operating systems. Rich earned his Ph.D. in Computer Science and Engineering from the University of Michigan in 1995.

Kevin J. Nowka received the B.S. degree in Computer Engineering from Iowa State University, Ames, in 1986 and the M.S. and Ph.D. degrees in Electrical Engineering from Stanford University in 1988 and 1995, respectively.

He joined the IBM Austin Research Laboratory in 1996 where he has conducted research on high-frequency microprocessors and low-power system-on-a-chip designs.

He currently manages the Exploratory VLSI Design department of the IBM Austin Research Laboratory. His current research includes power-efficient circuits for high-performance processors, power-efficient wireline communications, and process characterization circuits.

Pradip Bose received his B.Tech (Hons.) degree in electronics and electrical communication engineering from I.I.T Kharagpur, India in 1977 and his M.S. and Ph.D degrees in electrical and computer engineering from University of Illinois at Urbana-Champaign in 1981 and 1983 respectively.

He joined IBM T. J. Watson Research Center in 1983, where he currently manages a group on reliability- and power-aware microarchitectures. His research interests are in computer architecture, power-performance evaluation and fault-tolerant computing.

Sani Nassif received his PhD from Carnegie-Mellon university in the eighties. He worked for ten years at Bell Laboratories on various aspects of design and technology coupling including device modeling, parameter extraction, worst case analysis, design optimization and circuit simulation. He joined the IBM Austin Research Laboratory in 1996 where he is presently managing the tools and technology department, which is focused on design/technology coupling.


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