Date: Sunday, August 20, 2006
Location: Memorial Auditorium, Stanford University.

Last Updated: June 8, 2006

8:00 - 9:00am Breakfast
 
9:00am-12:30pm Morning Tutorial

Moderator: Christos Kozyrakis, Stanford University

Presentation: Multicore Programming: From Threads to Transactional Memory

Author(s):

Abstract:

All processor vendors have adopted multi-core designs as the best way to turn increasing transistor budgets into scalable performance. To deliver on their potential, multi-core chips require parallel applications. This tutorial will review parallel programming techniques for multi-core systems ranging from current industrial practices to promising research directions. First, we discuss multithreading techniques, including basic concepts, programming models, libraries, and tools for debugging and performance tuning. Next, we describe transactional memory, a research technology that brings the idea of database transactions to parallel programming. Apart from the basic concepts and implication to parallel programming, we will review hardware, software, and hybrid implementations of transactional memory on multi-core chips.
12:30-1:30pm Lunch

1:30-5:00pm

Afternoon Tutorial

Moderator: Jan Rabaey, UC Berkeley

Presentation: Wireless in the Home - Challenges and Opportunities

Abstract:

In the past decade, we have seen tremendous progress in the world of wireless networking. On the one side, wireless LANs are making it possible to transmit multimedia streams at unprecedented levels of fidelity and quality. We project that new developments such as cognitive radio will make wireless data rates within the home virtually unlimited. On the other hand, wireless sensor networks have emerged as a premier way of establishing distributed environment management and control. Yet, both areas are suffering from challenges in deployability, maintenance, scalability and most of all, user-friendliness.

In this tutorial, it is argued that the combination of the two is what is needed for the establishment of a truly user-aware and user-centric smart home environment (very often called ambient intelligence). By bridging the various networks currently operational in the home (voice, data, multimedia, control, security), an entirely new and more effective experience can be created.

In the tutorial, we will first outline the state of the art in wireless networking in both the high and the low data rate arenas. We will further discuss some developments that may shape the wireless home arena of the future.
In the second part of the tutorial, we will outline the key requirements of what it would take and propose both a flexible infrastructure and a set of service abstractions that encompass these requirements. It will be shown that the computational needs of such an environment translate into a formidable set of challenges for the semiconductor and SoC communities in terms of performance, power and cost.

Authors Bio

Yuan Lin is a Senior Staff Engineer from the Scalable Systems Group of Sun Microsystems. He works on compilers and tools for developing multi-threaded applications and is the project lead of a race detection tool project at Sun. Yuan is a member of the language committee for the next version of OpenMP specification. He received a PhD in Computer Science from the University of Illinois at Urbana-Champaign in 2000.

Christos Kozyrakis is an assistant professor of Electrical Engineering & Computer Science at Stanford. His research focuses on architectures, compilers, and programming models for parallel computer systems. He is currently working on transactional memory techniques that can greatly simplify parallel programming for the average developer.

Ali-Reza Adl-Tabatabai is a principle engineer in the Programming Systems Lab at Intel Corporation. He leads a team developing compilers and scalable runtimes for future Intel Architectures. His current research concentrates on language features supporting parallel programming for future multi-core architectures.

Bratin Saha is a senior staff researcher in the Programming System Lab at Intel Corporation. He is one of the architects for synchronization and locking in the next generation IA-32 processors. He is currently involved in the design and implementation of a highly scalable runtime for multi-core processors. As a part of this he has been looking at language features, such as transitional memory, to ease parallel programming.

Jan M. Rabaey received the EE and Ph.D degrees in applied sciences from the Katholieke Universiteit Leuven, Belgium, respectively in 1978 and 1983. From 1983 till 1985, he was connected to the University of California, Berkeley as a Visiting Research Engineer. From 1985 till 1987, he was a research manager at IMEC, Belgium, and in 1987, he joined the faculty of the Electrical Engineering and Computer Science department of the University of California, Berkeley, where he is now holds the Donald O. Pederson Distinguished Professorship. He has been a visiting professor at the University of Pavia (Italy), Waseda University (Japan), Technical University Delft (Netherlands), Victoria Technical University and the University of New South Wales (Australia).

He was the associate chair of the EECS Dept. at Berkeley from 1999 till 2002, and is currently the Scientific co-director of the Berkeley Wireless Research Center (BWRC), as well as the director of the GigaScale Systems Research Center (GSRC). He is an IEEE Fellow.

His main research interests include the conception and implementation of next-generation integrated wireless systems. This includes the analysis and optimization of communication algorithms and networking protocols, the study of ultra low-energy implementation architectures and circuits, and the supporting design automation environments.


Copyright© HOT CHIPS, 2006. All rights reserved.
All trademarks property of their owners. Valid HTML & CSS.