Home

Author(s): Chuck Moore, AMD; Craig Hampel, Rambus; Jerry Bautista, Intel; Fritz Kruger, AMD

Presentation: High Bandwidth Memory Technology & Systems Implications.

Abstract: As multicore CPUs and manycore GPUs continue to rapidly double their processor counts, the challenge is to develop mainstream application software that inherently scales its parallelism to leverage ever more processor cores. The CUDA scalable parallel programming model provides readily understood abstractions - a hierarchy of thread groups, shared memories, and barrier synchronization - that provide a clear parallel structure to conventional C code for one thread of the hierarchy. Learn how developers have made a wide range of CUDA applications scale transparently to hundreds of processor cores and thousands of concurrent threads. CUDA is a minimal extension of C/C++ applicable to both GPUs and CPUs.

• Introduction & Motivating Issues (Chuck Moore, AMD)
• Terabyte Bandwidth Initiative - Architectural Considerations for Next-Generation Memory Systems (Craig Hampel, Rambus)
• Tera-scale Computing and Interconnect Challenges – 3D Stacking Considerations (Jerry Bautista, Intel)
• System Architecture Implications and Perspective (Fritz Kruger, AMD)

1:30 - 5:00pm

Author(s):Ian Buck, Michael Garland, Patrick Legresley, Massimiliano Fatica, NVIDIA; Wen-mei Hwu, Univ. of Illinois

Presentation: Scalable Parallel Programming with CUDA.

Abstract: As Moore's Law enables us to pack more CPUs and other computing devices onto future chips, addressing the "Memory Wall" takes on a whole new level of importance. The combination of larger working sets, multiple working sets, and bandwidth hungry offload computing devices take a difficult situation and make it worse. This tutorial will introduce these challenges, and present several potential technology solutions, as well as the associated system-level implications.