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Efficient Fetch Mechanism by Employing Instruction Register
Mochamad Asri, Tokyo Institue of Technology
In general, Embedded Processors have substantially strict design constraints. Those constraints are space, power, and performance which often have conflicting design requirement. It is well-known that engineers face formidable problems to improve one constraint without negatively affecting others. Performance must be sufficient to meet the timing constraints whereas power consumption should be minimized, often to be less than a specified target. Moreover, the size of read-only-memory (ROM) may have rigid limits to minimize cost.
Instruction Register (IR) is proposed to deal with this trade-off (Hines et al, ISCA 2005). Instruction Register is a register file that stores the most frequently executed instructions. In the previous work, Hines et al used 32-entry IR combined with alteration of micro architecture and compiler support. With these techniques, they deliberately succeeded in reducing power consumption as well as code size.
In this paper, we proposed a novel architecture which combines large entry of IR along with unique binary translation to aim more efficient fetch mechanism that leads to further reduction of the code size and power consumption.
From processor simulation result, we found that the proposed method succeeded in reducing code size up to about 50% of conventional processor.
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