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The Maven Vector-Thread Architecture

Yunsup Lee, Rimas Avizienis, Alex Bishara, Richard Xia, Derek Lockhart, Christopher Batten and Krste Asanovic, UC Berkeley

Vector-threading is a novel architectural design pattern for data-parallel accelerators that attempts to combine the flexibility of multithreaded programming with the efficiency of vector execution. VT provides many control threads that each manage their own array of microthreads. The control thread uses vector memory instructions to efficiently move data and vector fetch instructions to broadcast scalar instructions to all microthreads. These vector mechanisms are complemented by the ability for each microthread to direct its own control flow. In this poster, we introduce the Maven VT Processor, which is a new VT implementation focused on simplifying the instruction set, microarchitecture, and programming methodology as compared to earlier VT implementations. Maven unifies the VT control-thread and microthread instruction sets and extends a traditional vector-SIMD microarchitecture with the minimal number of changes to enable VT execution. We use an explicitly data-parallel C++ programming methodology to compile a range of both regular and irregular data-parallel kernels. We study several microarchitectural optimizations including banked register files, per-bank integer ALUs, density-time execution, dynamic fragment convergence, and dynamic memory coalescing.

Using full VLSI implementations of many design points, we compare a Maven VT tile (i.e., several cores and first-level caches) to MIMD and vector-SIMD tiles. We find that a Maven VT tile provides greater efficiency than MIMD tiles, even on fairly irregular kernels, and improves programmability and efficiency compared to the traditional vector-SIMD tiles.

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