HC03 (1991)

General Information

HOT CHIPS 3 (1991)
Date August 26-27, 1991
Place Memorial Hall Auditorium, Stanford University
Program Final Program PDF
Committees Organizing and Program Committees PDF

Conference Day One

Session Monday, August 26, 1991
Opening Remarks
General Chair: Martin Freeman PDF
Program Co-Chairs:  Forest Baskett, John Hennessey
Session 1
High Performance Processors – I  
Chair:  John Hennessey, Stanford UniversitySuperSPARCTM : A Fully Integrated Superscalar Processor, Greg Blanck, Sun Microsystems, Steve Krueger, Texas Instruments. PDF

MlPS R4000 Technical Overview, Earl Killian, MlPS Computer Systems PDF

PA-RISC Processor for “Snakes” Workstation, Charles Kohlhardt, Hewlett Packard PDF

Session 2
Highly Parallal Chips
Chair: Martin Freeman, Philips Research
The LIFE Family of High-Performance Single Chip VLlWs, Gerrit Slavenburg and Yen Lee, Philips Research Palo Alto
Andrew Huang, CMU PDF

The Message-Driven Processor, William Dally, J. Stuart Fiske, Waldemar Horwat, John Keen, Richard Lethin, Michael Noakes and Peter Nuth MIT Artificial Intelligence Laboratory
D. Scott Wills, University of Central Florida
Andrew Chien, University of Illinois
Salim Ahmed, Paul Carridc, Roy Davison, Greg Fyler
Steve Lear, Mark Vestrich and Teg Nguyen, Intel PDF

The TRW CPUAX Superchip, A. Miscione, R. Almeida, H. Hennecke and R. Mann TRW Electronics and Technology Division PDF

Session 3 
High-Performance Processors – 2
Chair:  Forest Baskett, Silicon GraphicsAn 80 MHz 64-Bit Floating Point RISC Processor
with Direct DRAM Support
, James Hesson, Micron Technology PDF

The i860TM XP: 2nd Generation of the i860TM
Supercomputing Microprocessor Famlly
,David Perlmutter and Michael Kagan, Intel Israel PDF

Beyond Claims of Free Transistors and Abundant Instruction-Level Parallelism , Michael Smith, Stanford University PDF

Session 4 
Low Power and Low Cost
Chair: Alan Smith, U.C. BerkeleyTera microCORE Chipset, Greg Favor, Tera Microsystems PDF

The SparKITTM Chipset, Mohammed Wadi, LSI Logic Corporation PDF

SPARCore Modules, Raju Vegesna, Ross Technology PDF

7:30 Evening Panel Session
Five Instructions Per Clock: Truth or Consequences
Session Chairs: Alan Smith, U.C. Berkeley and
John Mashey, MlPS Computer Systems
Panelists: Joseph A Fisher, Hewlett Packard Laboratories; Norm Jouppi, DEC Western Research Lab;
Monica Lam, Stanford University;
James Smith, Cray Research;
David Wall, DEC Western Research Lab

Conference Day Two

Session Tuesday, August 27, 1991
Session 5 
Chair:  Teresa Meng, Stanford University

A GaAs 200 Mbps 64×64 Crosspoint Chip, Ron Cates, Vitesse Semiconductor PDF

An Enhanced Crossbar Router Chip for a Shared Memory
, Henry Minsky, Tom Knight and Andre DeHon, MIT Al Lab PDF

The NEURON Chip Family Architecture, Robert Dolin, Echelon PDF

The Protocol Engine Chipset,  Des Young, Protocol Engines PDF

Session 6 
11:00 -12:30
Caches and Floating Point
Chair:  John Crawford, IntelMlPS R4000 Caches and Coherency, Paul Ries, MlPS Computer Systems PDF

The Megacell Differentiated Floating Point Product Family, Merrick Darley, Don Steiss, Peter Groves, David Bural
Maria Gill and Tod Wolf, Texas Instruments PDF

82495DX/82490DX: A High-Performance 2nd Level Cache
for the i486TM DX CPU
, Adi Gobert, lntel Corporation PDF

Session 7 
Special Processors 
Chair:  John Mashey, MlPS Computer System

A Smart Frame Buffer, Joel McCormack, DEC Western Research Laboratory Bob McNamara and Lindsay Gage, DEC PDFCNAPS (Connected Network of Adaptive ProcessorS), Dan Hammerstrom and Gary Tahara, Adaptive Solutions PDF
SMM, The “Virtual 386TM “, Dave Vannier, lntel PDF

Session 8 
High-Performance Processors – 3 
Chair:  Dave Ditzel, Sun MicrosystemsNational’s Swordfish – A Superscalar with DSP,  Reuven Marko and Motti Beck, National Semiconductor PDF

T9000 – Superscalar Transputer
, Bob Krysiak, Richard Forsyth and Roger Shepherd  INMOS Ltd. – SGS-Thomson Microelectronics PDF
5:00 Closing Remarks