HC04 (1992)

Date August 9-11, 1992
Place Memorial Auditorium, Stanford University
Program Final Program PDF
Committees Organizing and Program Committees


Tutorials Sunday, August 9, 1992
Morning Tutorial
A Quantitative Approach to Microprocessor Architecture (Part 1) 
Chair: Professor Mark D. Hill
Afternoon Tutorial
A Quantitative Approach to Microprocessor Architecture (Part 2) 
Chair: Professor Mark D. Hill 

Conference Day One

Session Monday, August 10, 1992
Opening Remarks
General Chair: Glen Langdon PDF
Program Co-Chairs: David Patterson, John Mashey PDF
Session 1
High Performance Processors (Part 1) 
Chair: David Patterson, University of California, Berkeley
DEC Alpha Architecture and 21064 Chip, E. McLellan (Digital Equipment Corporation) PDF

A 200 MFLOP HP PA-RISC Processor, W. Jaffe, B. Miller, J. Yetter (Hewlett-Packard) PDF

Session 2
Multiprocessor Interface Issues 
Chair: Ruby Lee, Hewlett-Packard
Multiprocessor Features in a PA-RISC Processor Interface Chip, T. Alexander, K. Chan, C. Hu, N. Noordeen, S. Ziai (Hewlett-Packard) PDF

On-Chip Cache Hierarchy for 1000-MIPS Multi-Superscalar Processors, T. Nishimukai, M. Hanawa, O. Nishii, M. Suzuki, K. Yano, M. Hiraki (Hitatchi) PDF

Sparcle: Today’s Micro for Tomorrow’s Multiprocessor, A. Argarwal (MIT)

Session 3
Low Cost Processors 
Chair: John Mashey, Silicon GraphicsHighly Integrated SPARC Processor Implementation, S. Joshi (Sun Microsystems) PDF

The LR33020 GraphX Processor: A Single Chip MIPS-RISC Based X Terminal Controller, S. Desai (LSI Logic) PDF

The ARM600 Processor and FPA, M. Muller (Advanced RISC Machines)

Session 4
Low Power Systems 
Chair: Dave Ditzel, Sun MicrosystemsA VLSI Chip Set for Personal Communications Systems, R. Scauzzo (AT&T Bell Labs) PDF

SPARC90 – Chipset on a Chip, J. Pendleton (Sun Microsystems) PDF

Cold Chip Design Techniques, R. Broderson, A. Chandrakasan, S. Sheng (University of California, Berkeley) PDF

Panel Discussion
DRAM Choices for the ’90s: 1 Gigabyte/Second or Bust
Moderator: Skip Stritter, Silicon Graphics PDF
Rambus – M. Horowitz (Stanford)
Ramlink – D. James (Apple Computer)
Synchronous DRAM – W. Vokley (Texas Instruments)
Cache DRAM – C. Hart (Mitsubishi)

Conference Day Two

Session Tuesday, August 11, 1992
Session 5
Interfaces and Interrupts 
Chair: John Mashey, Silicon GraphicsThe SBus Goldchip, M. Sodos (Sun Microsystems) PDF

Peripheral Component Interconnect, D. Carson (Intel) PDF

Advanced Programmable Interrupt Controller (APIC) for MP and 32-bit Operating Systems, P.K. Nizar (Intel) PDF

Session 6
Vector and Video 
Chair: Dave Patterson, University of California, BerkeleyThe Vector Coprocessor (VU) for the CM-5, J. Wade (Thinking Machines Corp) PDF

A 289 MFLOPS Single Chip Supercomputer, C. Lund for H. Lino, H. Takahashi, T. Sukemura, M. Kimura, K. Fukita, S. Mori (Fujitsu) PDF

A Programmable Solution for Standard Video Compression, J. Fandrianto, T. Williams (Integrated Information Technology) PDF

Session 7
Electrons, Photons, and Neurons 
Chair: Teresa Meng, Stanford University

Chip Pair Creates Self-Timed Network Fabirc for Paragon Parallel Supercomputers, R. Traylor, D. Dunning (Intel Supercomputer Systems) PDF 

GaAs VLSI Enhancement through Utilization of Global Optical Free Space ‘Smart’ Interconnects, P. Guifoyle, F. Zeise (OptiComp Corp) PDF

Silicon Based Nerve Interfaces, G. Kovacs (Stanford University) PDF

Session 8 
High Performance Processors (Part 2) 
Chair: Uri Weiser, IntelThe Second Generation SPARCore Mbus Chip, M. Guiterrez (Ross Technology) PDF

Superscalar Architecture of the P5 – X86 Next Generation Microprocessor, D. Alpert (Intel) PDF

The P5 Floating-Point Unit, D. Avnon (Intel) PDF