HC06 (1994)

Date August 14-16, 1994
Place Memorial Auditorium, Stanford University
Program Final Program PDF
Committees Organizing and Program Committees


Tutorials Sunday, August 14, 1994
Morning Tutorial
Algorithms and Hardware for Video Compression 
Chair: Teresa H. Meng, Stanford University
Afternoon Tutorial
Instruction-Set Extensions for Multiprocessor Interconnects 
Chair: David V. James, Apple Computer, Inc.

Conference Day One

Session Monday, August 9, 1994
Opening Remarks
General Chair: John Mashey PDF
Program Co-Chairs: Don Alpart, Alan Jay Smith PDF
Session 1
CPUs (Part 1) 
Chair: Norman P. Jouppi, DEC WRL
An Overview of the 21164 Alpha AXP Microprocessor, John Edmondson, Paul Rubinfeld (Digital Equipment Corp) PDFThe Power2+ Processor, David Shippy (IBM) PDF

A 500MHz 32b 0.4um CMOS RISC Processor (Gallop), Kazumasa Suzuki (NEC) PDF

Session 2
Multiprocessors and Encryption 
Chair: Howard Sachs, Sun Microsystems
The Alewife CMMU: Addressing the Multiprocessor Communications Gap, John Kubiatowicz (MIT) PDFnCube3 Integrated MPP Node Processor, Robert Duzett (nCube) PDF

A 100Kbit/sec Single Chip: Modular Exponentiation Processor, Holger Orup (Aarhus University, Denmark) PDF

Session 3 
Networks, Communication
 Forest Baskett, Silicon GraphicsUAI2110: A Universal GaAs ATM Interface Chip for High Speed Networks, Premysl Vaclavik (Thomas Neuroth GmbH, Austria) PDF

A 500MHz BICOM GByte/Second SCI-Link Implementation, Wayne Nation (IBM) PDF

The STC104 Asynchronous Packet Switch, Peter Thompson (INMOS Ltd.) PDF

Session 4 
CPUs (Part 2) 
Chair: Don Alpert, Intel CorporationThe New I960 CPU That Offers More for Less, The P100, Richard Brunner, Delf Atallah (Intel) PDFSH-II: A Low Power RISC Micro for Consumer Applications, Shumpei Kawasaki (Hitatchi) PDF
Panel Discussion
The Investor (Venture) Community View of What’s Hot 
Moderators: Forest Baskett, Silicon Graphics
Cliff Friedman (Bear Steams)
Stephen Shapiro (Tiger Management)
Peter Thomas (Institutional Venture Partners)

Conference Day Two

Session Tuesday, August 16, 1994
Session 5
Chair: Allen Baum, Apple Computer, Inc.82430NX PCIset: Companion to the Highest Performance Pentium Processor, Patrick Correia (Intel) PDF

A Power PC/PCI Bridge Chip with a Cache and Memory Controller, Karl Wang (Motorola) PDF

Session 6
Chair: Ruby Lee, Hewlett-PackardAn ASIC for Interactive 3D Graphics, Stephanie Winner (Apple Computer)GLiNT – A 3D Graphics Processor Based on the OpenGL Standard, Neil Trevett (3Dlabs)

The Smart Frame Buffer Goes Hollywood: 3D and TV, Joel McCormack (Digital Equipment Corp)

A Cached VRAM for 3D Graphics, Michael Deering (Sun Microsystems)

Session 7
Chair: Anoop Gupta, Stanford UniversityVideo Compression Processor for H.320-to-Indeo Transcoding, Bryan Martin (Integrated Information Technology)

A High Performance Programmable Multistadard Video Compression Chip Set, David Still (Array Microsystems)

Multimedia Enhancements for PA-RISC Processors, Ruby Lee (Hewlett-Packard)

Session 8 
CPUs (Part 3) 
Chair: Alan J. Smith, University of California, BerkeleyPowerPC 604, Marvin Denman (Motorola) PDFThe Thunder SPARC Processor, Bruce Lightner (Metaflow Technologies) PDF

The Superscalar Hardware Architecture of the MC68060, Joe Circello (Motorola) PDF

A High Performance, Low Power, Pentium Processor, Doug Carmean, Lawrence Clark, Robert Rozploch (Intel)