HC19 (2007)

General Information

HOT CHIPS 19 (2007)

Date August 19-21, 2007
Place Memorial Auditorium, Stanford University
Committees Organizing and Program Committees PDF


TutorialsSunday, August 19, 2007

Morning Tutorial Chair: Ralph Wittig, Xilinx

  • Approaches to System Design for the Working Engineer.
  • Part I: ASICs To ASSPs For Working Engineers (Building the OMAP 3430) PDF
    Author: David Witt, Texas Instruments
  • Part II: 20 Years Of FPGA Evolution: From Glue Logic To Systems Components PDF
    Author: Peter Alfke, Xilinx
  • Part III: Exploiting Processor Heterogeneity Through Reconfigurable Interactions PDF
    Author: Shepard Siegel, Mercury Computer Systems
Afternoon Tutorial Chair: Norm Jouppi, Hewlett Packard

  • Enterprise Power and Cooling: A Chip-to-Data Center Perspective. 
    Part I: Background
    Part II
    : Cooling: A Chip-Core to Cooling-Tower Perspective
    Part III
    : Power: From Chips to Data Centers
    Part IV
    : Case Study and Future Directions
    Author(s): Chandrakant Patel and Parthasarathy Ranganathan, HP Labs

Conference Day One

SessionMonday, August 20, 2007

Opening Remarks Opening remarks
Session 1 IBM Power6™
Chair: Doug Burger, University of Texas – Austin
• Fault-Tolerant Design of the IBM POWER6™ Microprocessor.
Authors(s): Kevin Reick, Pia N. Sanda, Scott Swaney, Jeffrey W. Kellington, Michael Floyd (IBMPDF• System Performance Scaling of IBM POWER6™ Based Servers.
Authors(s): Jeff Stuechell (IBMPDF

 The 3rd Generation of IBM’s Elastic Interface (EI-3) Implementation of POWER6™.
Authors(s): Daniel Dreps (IBMPDF

Keynote 1 Digital Gaia
 Gordon Garb, Sun Microsystems
Author(s): Vernor Vinge, Computer scientist, science-fiction writer, author of True Names and Rainbows End.
Session 2 Multi-Core and Parallelism I
Chair: Marc Tremblay, Sun Microsystems
• NVIDIA GeForce 8800™ GPU.
Author(s): Erik Lindholm, Stuart Oberman (NVIDIAPDF• NVIDIA GPU Parallel Computing Architecture.
Author(s): John Nickolls (NVIDIAPDF

• Performance of Non-Graphics Applications on the GeForce 8800™and the CUDA™ Parallel-Programming Environment.
Author(s): Wen-Mei Hwu (UIUC), David Kirk (NVIDIA), Shane Ryoo (UIUC), John A. Stratton (UIUC), Kuangwei Hwang (UIUCPDF

Session 3 Multi-Core and Parallelism II
Chair: Alan Jay Smith, UC Berkeley• Radeon R600, a 2nd Generation Unified Shader Architecture.
Author(s): Michael Mantor (AMDPDF• Teraflop Prototype Processor with 80 Cores.
Author(s): Yatin Hoskote, Sriram Vangal, Nitin Borkar, Shekhar Borkar (IntelPDF

• Design and Implementation of the TRIPS Prototype Chip.
Author(s): Madhu Sravana Sibi Govindan, Doug Burger, Steve Keckler (U Texas AustinPDF

• Tile Processor: Embedded Multicore for Networking and Multimedia.
Author(s): Anant Agarwal, Liewei Bao, John Brown, Bruce Edwards, Matt Mattina, Chyi-Chang Miao, Carl Ramey, David Wentzlaff (Tilera CorporationPDF

Session 4 Embedded and Video
Chair: Jan-Willem Van de Waerdt, NXP• SH-X3: SuperH Multi-Core for Embedded Systems.
Author(s): Shinichi Shibahara (Renesas), Masashi Takada (Hitachi), Tatsuya Kamei, Kiyoshi Hayase, Yutaka Yoshida, Osamu Nishii, Toshihiro Hattori (RenesasPDF• An HD Image Processor for Low-Cost Entertainment Products.
Author(s): Deepu Talla (Texas InstrumentsPDF

• A Professional H.264/AVC CODEC Chip-Set for HDTV Broadcast Infrastructure and High-End Flexible CODEC Systems.
Author(s): Mitsuo Ikeda, Hiroe Iwasaki, Koyo Nitta, Takayuki Onishi, Takeshi Sano, Atsushi Sagata, Yasuyuki Nakajima, Minoru Inamori, Takeshi Yoshitome, Hiroaki Matsuda, Ryuishi Tanida, Atsushi Shimizu,Jiro Naganuma (NTTPDF

Panel Discussion What’s Next After CMOS?
Moderator: Norm Jouppi, Hewlett Packard
John Kubiatowicz (UC BerkeleyPDF
Mike Mayberry (IntelPDF
Mark Horowitz (Stanford UniversityPDF
Stan Williams (Hewlett PackardPDF
Ghavam Shahidi (IBMPDF

Conference Day Two

SessionTuesday, August 21, 2007

Session 5 Session Five: Technology and Software Directions
Chair: Raj Amirtharajah, UC Davis Multi-terabit Switch Fabrics Enabled by Proximity Communication.
Author(s): Hans Eberle (SunPDF Thyristor RAM: A High-Speed High-Density Embedded Memory.
Author(s): Farid Nemati (T-RAM SemiconductorPDF

• Raksha: A Flexible Architecture for Software Security.
Author(s): Hari Kannan, Michael Dalton, Christos Kozyrakis (Stanford UniversityPDF

Session 6 Wireless
Chair: Forest Baskett, New Enterprise Associates• A 4Gbps Wireless Uncompressed 1080p 60 GHz HD Transceiver.
Author(s): Jeff Gilbert (SiBEAMPDF• A 2×2 MIMO Baseband for Wireless Local-Area Network (802.11n).
Author(s): Jason A. Trachewsky (BroadcomPDF
Keynote 2 Multicore and Beyond: Evolving the x86 Architecture
 Chuck Moore, AMD
Author(s): Phil Hester, AMD (CTO) PDF
Special Presentation Chair: John Montrym, NVIDIA
• Wireless broadband and entrepreneurship in America.
Author(s): Reed Hundt (Vice Chair, Frontline Wireless; Former Chair, FCCPDF
Session 7 Networking
Chair: Dileep Bhandarkar, Microsoft• Chesapeake: A 50Gbps Network Processor and Traffic Manager.
Author(s): Brian Alleyne (Bay MicrosystemsPDF• A System-on-a-Chip with Integrated Accelerators.
Author(s): Rumi Zahir (IntelPDF

• Focalpoint II, A Low-Latency, High Bandwidth Switch/Router Chip.
Author(s): Uri Cummings, Mike Zeile (Fulcrum MicrosystemsPDF

Session 8 Mobile PC Processors and Chipsets
Chair: Christos Kozyrakis, Stanford University• Power Management Features in Penryn 45nm Core2™ Duo.
Author(s): Varghese George (IntelPDF• Next Generation Mobile x86 Processor.
Author(s): Jonathan Owen (AMDPDF

• nForce 680i and 680 Platform Processors.
Author(s): Brian Langendorf (NVIDIAPDF

Session 9 Big Iron
Chair: John Montrym, NVIDIA• VictoriaFalls – Scaling Highly-Threaded Processor Cores.
Author(s): Stephen Phillips (SunPDF• The Next-Generation Mainframe Microprocessor.
Author(s): Charles Webb (IBMPDF