HC27 (2015)

Flint Center, Cupertino, CA, Sunday-Tuesday, August 23-25, 2015.

Full Program Zipfile (130MB)

At A GlanceTutorialsConf. Day1Conf. Day2Posters
  • Sunday 8/23: Tutorials
    • 8:00 AM – 9:00 AM: Breakfast
    • 9:00 AM – 12:15 PM: Deep Learning
    • 12:15 PM – 1:30 PM: Lunch
    • 1:30 PM – 5:35 PM: Makers from Hobbyists to Professionals
    • 5:45 PM – 7:00 PM: Wine and Cheese Reception
  • Monday 8/24: Conference Day 1
    • 8:15 AM – 9:15 PM: Breakfast
    • 9:15 AM – 11:00 AM: IoT
    • 11:30 AM – 12:30 PM: Keynote 1:
    • 12:30 PM – 1:45 PM: Lunch
    • 1:45 PM – 3:45 PM: Multimedia and Signal Processing
    • 4:15 PM – 6:15 PM: HPC and Cloud
    • 6:15 PM – 7:15 PM: Reception
  • Tuesday 8/25: Conference Day 2
    • 7:30 AM – 8:30 AM: Breakfast
    • 8:30 AM – 10:00 AM: FPGAs
    • 10:30 AM – 12:00 PM: GPUs
    • 12:00 PM – 1:15 PM: Lunch
    • 1:15 PM – 2:15 PM: Keynote 2: 5G
    • 2:45 PM – 4:15 PM: Applications
    • 4:45 PM – 6:45 PM: Processors
    • 6:45 PM – 7:00 PM: Closing Remarks


Sun 8/23 Tutorial Title Presenter Affiliation
8:00 AM Breakfast
9:00 AM Deep Learning Architectures, algorithms and applications Roland Memisevic University of Montreal
10:30 AM Break
10:45 AM Deep Learning Common software tools, research questions, outlook  Roland Memisevic University of Montreal

12:15 PM Lunch
1:30 PM Makers from Hobbyists to Professionals Welcome Christopher Nitta UC Davis
1:40 PM Maker Trends: The Path of Least Resistance Peter Dokter SparkFun
2:35 PM IoT Device Development Challenges and Solutions Venkat Mattela and Sailaja Dharani Redpine Signals
3:30 PM Break
3:45 PM Makers (cont) Implementing Software Defined Radio on the Parallella Andreas Olofsson Adapteva
4:40 PM Current trends for hardware & software developers Vrajesh Bhavsar ARM
5:35 PM Wrap Up

5:45 PM Wine & Cheese Reception
7:00 PM End of Reception

Conference Day 1

Mon 8/24 Session Title Presenter Affiliation
8:15 AM Breakfast
9:15 AM Welcome Introductory Remarks
9:30 AM Internet of Things PULP: A Parallel Ultra-Low-Power Platform for Next Generation IoT Applications 1Davide Rossi, 1Francesco Conti, 1,2Andrea Marongiu, 2Antonio Pullini, 1Igor Loi, 2Michael Gautschi, 1Giuseppe Tagliavini, 2Alessandro Capotondi, 3Philippe Flatresse and 1,2Luca Benini 1DEI, 2ETH, 3ST Micro
Design of an Ultra-low Power SoC Testchip for Wearables & IOT May Wu, Ravishankar Iyer, Yatin Hoskote, Steven Zhang, Bernard Deadman, Mukesh Bhartiya and Yada Satish Intel
Ultra-Low Power Wireless SoCs Enabling a Batteryless IoT Benton Calhoun and David Wentzloff PsiKick

11:00 AM Break
11:30 AM Keynote 1 Convolutional Neural Networks Yann LeCun Facebook

12:30 PM Lunch
1:45 PM Multimedia and Signal Processing Architecture of the V6x Hexagon DSP for Mobile Imaging and Always-On Applications Lucian Codrescu, Eric Mahurin, Mao Zeng, Erich Plondke, Suresh Venkumahanti and Rick Maule Qualcomm
A Scalable Heterogeneous Multicore Architecture for ADAS Zoran Nikolic, Rama Venkatasubramanian, Jason Jones and Peter Labaziewicz TI
Energy Efficient Graphics and Multi-media in 28nm Carrizo APU Guhan Krishnan, Dan Bouvier, Praveen Dongara and Louis Zhang AMD
Revisiting DSP Acceleration with the Kalray MPPA Manycore Processor Benoît Dupont de Dinechin Kalray

3:45 PM Break
4:15 PM High Performance, Cloud Computing and Communication Mars: A 64-Core ARMv8 Processor Charles Zhang Phytium
LS2085A Freescale’s new QorIQ Layerscape Communications Processor John Xu and Sam Fuller Freescale
Oracle’s Sonoma Processor: Advanced low-cost SPARC processor for enterprise workloads Basant Vinaik and Rahoul Puri Oracle
I/O Virtualization and System Acceleration in Power8 Michael Gschwind IBM

6:15 PM Reception
7:15 PM End of Reception

Conference Day 2

Tue 8/25 Session Title Presenter Affiliation
7:30 AM Breakfast
8:30 AM FPGAs Xilinx 16nm UltraScale+ MPSoC and FPGA Families Vamsi Boppana, Sagheer Ahmad, Ilya Ganusov, Vinod Kathail, Vidya Rajagopalan and Ralph Wittig Xilinx
Stratix 10 Altera’s 14nm FPGA Targeting 1GHz Performance Mike Hutton Altera
Toward Accelerating Deep Learning at Scale Using Specialized Logic Kalin Ovtcharov, Olatunji Ruwase, Joo-Young Kim, Jeremy Fowers, Karin Strauss and Eric Chung Microsoft Research

10:00 AM Break
10:30 AM GPUs MIAOW – An Open Source GPGPU Raghu Balasubramanian, Vinay Gangadhar, Ziliang Guo, Chen-Han Ho, Cherin Joseph, Jai Menon, Mario Drumond, Robin Paul, Pradip Valathol and Karu Sankaralingam University of Wisconsin
AMD’s next Generation GPU and Memory Architecture Joe Macri, Raja Koduri, Mike Mantor and Bryan Black AMD
The ARM Mali-T880 Mobile GPU Ian Bratt ARM

12:00 PM Lunch
1:15 PM Keynote 2 The Road to 5G Matt Grob CTO, Qualcomm

2:15 PM Break
2:45 PM Applications Professional H.265/HEVC Encoder LSI Toward High-Quality 4K/8K Broadcast Infrastructure Hiroe Iwasaki, Takayuki Onishi, Ken Nakamura, Koyo Nitta, Takashi Sano, Yukikuni Nishida, Kazuya Yokohari, Jia Su, Naoki Ono, Ritsu Kusaba, Atsushi Sagata, Mitsuo Ikeda and Atsushi Simizu NTT
Ultra-low-light CMOS Biosensor Helps Tackle Infectious Diseases Zhimin Ding Anitoa
Five-Speed PHY Enables 2.5Gbps and 5Gbps Ethernet Rates Over Legacy Copper Cables Ramin Shirani & Ramin Farjadrad Aquantia

4:15 PM Break
4:45 PM Processors Knights Landing: 2nd Generation Intel “Xeon Phi” Processor Avinash Sodani Intel
Intel “Xeon” Processor D: The first Xeon processor optimized for dense solutions Dheemanth Nagaraj and Chris Gianos Intel
Raven: A 28nm RISC-V Vector Processor with Integrated Switched-Capacitor DC-DC Converters and Adaptive Clocking Yunsup Lee, Brian Zimmer, Andrew Waterman, Alberto Puggelli, Jaehwa Kwak, Ruzica Jevtic, Ben Keller, Stevo Bailey, Milovan Blagojevic, Pi-Feng Chiu, Henry Cook, Rimas Avizienis, Brian Richards, Elad Alon, Borivoje Nikolic and Krste Asanovic University of Berkeley
Intel Atom-X5/X7-8000 Series Processors, Codenamed Cherry Trail Steven Tu Intel

6:45 PM Closing Remarks

Posters (** = Awarded Best Poster of Conference)

Title Presenter
Anti-Virus in Silicon ** Adrian Tang, John Demme, Simha Sethumadhavan and Salvatore Stolfo of Columbia University
Lagopus FPGA – a reprogrammable data plane for high-performance software SDN switches. Koji Yamazaki, Yoshihiro Nakajima, Takahiro Hatano and Akihiko Miyazaki of NTT Labs
Why Microarchitecture Matters for Successful Security Library Implementations Sami Saab, Pankaj Rohatgi, Craig Hampel, Jeremy Cooper and Elke De Mulder of Cryptography Research
Comparison of Key/Value Store (KVS) in Software and Programmable Hardware John Lockwood of Algo-Logic
NMI: A New Memory Interface for Cellphones to Supercomputers David Roberts, Amin Farmahini-Farahani, Kevin Cheng, Nathan Hu and Michael Ignatowski of AMD Research
Flexible Video Processing Platform for 8K UHD TV Sukjin Kim, Young-Hwan Park, Jaehyun Kim, Minsoo Kim, Wonchang Lee and Shihwa Lee of Samsung
A Low-power and Real-time Augmented Reality Processor for the Next Generation Smart Glasses Gyeonghoon Kim and Hoi-Jun Yoo of Korea Advanced Institute of Science and Technology
Under 100-cycle Thread Migration Latency in a Single-ISA Heterogeneous Multi-core Processor Elliott Forbes, Zhenqian Zhang, Randy Widialaksono, Steve Lipa, Brandon Dwiel, Eric Rotenberg, W. Rhett Davis and Paul D. Franzon of North Carolina State University