Die Stacking


2.5D/3D die stacking increases aggregate inter-chip bandwidth and shrinks board footprint while reducing I/O latency and energy consumption. By integrating in one package multiple tightly-coupled semiconductor dice – each possibly in a process optimized for power, performance and costs for a particular function – this technology gives system designers additional options to partition and scale solutions efficiently.  Die stacking has already transformed the design of high-end CMOS image sensors, and it promises to also enhance FPGA, graphics and mobile applications.
In Part 1 of this tutorial we will examine the key enabling technologies such as silicon interposer, TSV, micro-bump and assembly integration.  In Part 2 we will cover the design considerations & trade-offs of 2.5D/3D in CAD, ESD and architecture.  Part 3 will showcase how the technology is used in systems and applications for memory integration, optics integration and monolithic die partitioning.


  • 2:00pm – 2:15pm: Introduction by Liam Madden from Xilinx
  • 2:15pm – 3:05pm: Technology
    • Fab, Interposer and TSV by Remi Yu from UMC
    • Assembly and Micro Bumps by Choon Lee from Amkor
  • 3:05pm – 3:55pm: Design Considerations
    • 3D, CAD and Floorplanning by Riko Radojcic from Qualcomm
    • 2.5D, CAD and ESD by Shankar Lakka from Xilinx
  • 3:55pm – 4:10pm: Break for refreshments
  • 4:10pm – 5:00pm: System Implications
    • Memory Consideration and Heterogeneous Die by Bryan Black from AMD
    • Optical Considerations by Ephrem Wu from Xilinx
  • 5:00pm – 5:30pm: Panel moderated by Liam featuring all the speakers

Tutorial Details and Bios

Liam Madden


Liam Madden is corporate vice president of FPGA Development and Silicon Technology at Xilinx. He has responsibility for FPGA design, Advanced Packaging (including Stacked Silicon Interconnect) and Foundry Technology. Madden joined Xilinx in 2008, bringing more than 25 years experience in a range of design and technology leadership positions with Digital Equipment Corp., MIPS Technologies, Inc., Microsoft Corp. (XBOX Division), and AMD.

Madden earned a BE from the University College Dublin and a MEng from Cornell University. He holds five patents in the area of technology and circuit design.

Remi Yu from UMC

Foundry TSV Enablement For 2.5D/3D Chip Stacking

For 2.5D/3D chip stacking applications, foundry has fully demonstrated fine-pitch high density TSV/RDL, leveraging the single/dual damascene Cu processes of advanced CMOS logic fab. This presentation reviews the critical steps of foundry TSV process, test results, applications and related ecosystem work models.


Remi Yu received the B.S. degree in electrophysics from National Chiao Tung University, Hsinchu, Taiwan in 1989. He is currently deputy director of corporate marketing at United Microelectronics Corporation, with focus on 3D IC and ecosystem marketing. Since joining UMC in 2004, he has worked on the foundry’s intellectual property marketing and customer design support. He became a member of the foundry’s 3D IC program team starting mid-2011 and has been working on UMC’s Open Ecosystem Initiative since. He worked at Macronix International Co., Ltd. prior to joining UMC.

Choon Lee from Amkor

Process Integration and Challenges in 2.5D and 3D TSV Assembly

Small productions in FPGA and Power amplifier applications show that the TSV technology is close to reality even though the supply chain of this technology is still in question. In my context, starting off TSV making in Si at the foundries, MEOL, BEOL and Assembly processes at the OSATs are passed through to be a product. In this talk the processes for MEOL, BEOL and Assembly will be outlined with the process challenges surfaced out. In addition, some issues related to infrastructure building including capacity will be discussed.


  • July 2012 – present : Head of Product Group
  • Jan 2010 – present : CTO for RnD and Process/Equipment Engineering
  • Feb 1996 – Dec 2009 : Team managers and Head of RnD
  • Aug 1986 – Jan 1993 : MS and PhD at Case Western Reserve University
  • Mar 1977 – Aug 1985 : BS and MS at Korea University, Marine Corp.

Riko Radojcic from Qualcomm


Riko Radojcic is a Director of Engineering at Qualcomm CDMA Technologies, and a leader of various Design-for-Technology initiatives; including Design-for-3D, Design-for-Thermal, Design-for-Manufacturability & Variability, Si-Package CoDesign, etc, and involving methodologies at polygon, circuit, logic, and/or system design levels.

Radojcic has more than thirty year’s experience in the semiconductor industry, specializing in the integration of process, design and EDA considerations, and design-for-Si solutions. Before joining Qualcomm, he was a consultant to semiconductor and EDA companies providing engineering and business development services focused on process-design integration. He was a director of business development and marketing for DFM Solutions at PDF Solutions, and a Business Manager and an Architect with Tality and Cadence, specializing in design technology integration and process characterization and modeling.

Radojcic has held a series of managerial and engineering positions with Unisys and Burroughs, in device engineering, failure analyses and reliability engineering areas. He began his career as a process engineer with Ferranti Electronics, UK.

Radojcic received his BSc and PhD degrees from University of Salford, UK.

Shankar Lakka from Xilinx

2.5D, CAD and ESD

Xilinx’s Stacked Silicon Interconnect (SSI) technology is used to connect multiple FPGAs or other IP die on a single Silicon Interposer. This presentation gives an overview of 3D IC-SSI Technology and Engineering challenges faced during the development of the 3D-IC products. Areas that will be covered are Timing, Physical and Electrical Verification, as well as Signal Integrity.


Shankar Lakka is the Director of IC Design for full chip FPGA Integration group at Xilinx Inc San Jose. He has been at Xilinx for over 16 years. Shankar has recently led the design and full chip Integration of Xilinx SSI devices. He holds 14 US Patents.

Bryan Black from AMD

 Memory Consideration and Heterogeneous Die

Since room sized computers, advances in technology have been utilized to increase performance reduce power and shrink form factors.  Historically new process and packaging technologies have been at the heart of this evolution of ever increasing performance density.   Performance density drives our industry creating new compute form factors and usage models for consumers.   Interposer and 3D are emerging as the next generation of technologies that will continue to drive performance density.   This talk will discuss how die stacking is required by the industry and outline its primary challenges.


Bryan Black received his Ph.D. from Carnegie Mellon.  With over 20 years of experience Black has had the honor of working at Motorola, Intel, and AMD.   He has done a little of everything from devices to circuits to microarchitecture to test to packaging.   Black is currently a Senior AMD Fellow and runs the AMD die stacking program.

Ephrem Wu from Xilinx

Optical Considerations

This talk presents a view of when optical interconnects will be prevalent in communications backplanes. It outlines design and supply-chain considerations for 3D-integrated photonics to play a key role in optical backplanes.


Ephrem Wu is Senior Director of Advanced Communications at Xilinx. He is responsible for advanced FPGA solutions for wireline and wireless communications infrastructure. He joined Xilinx in 2010 and led the design of the industry’s first heterogeneous FPGA. From 2000-2010, Ephrem was with Velio Communications and LSI (which acquired Velio in 2004), leading the definition and development of packet switches and network processors. Prior to Velio, he held various ASIC, circuit, and software design positions at SGI, Hewlett-Packard, Panasonic, and AT&T.

Ephrem earned a BSE degree from Princeton University and an MS degree at the University of California, Berkeley. Both degrees are in EE with an emphasis on computer-aided design. He holds nine patents in switch architecture and circuit design.