HC25 Program

Tutorials | Conference | Posters

Memorial Auditorium, Stanford, CA
Sunday-Tuesday, August 25-27, 2013.

 

Tutorials

Heterogeneous System Architecture (HSA): Overview and Implementation. Heterogeneous computing is emerging as a requirement for power-efficient SOC design: modern chips no longer rely on a single general-purpose processor, but instead benefit from specialized processors tailored for each task. Traditionally these specialized processors have been difficult to program due to separate memory spaces, kernel-driver-level interfaces, and specialized programming models. The Heterogeneous System Architecture (HSA) aims to bridge this gap by providing a common system architecture, and a basis for designing common higher-level programming models for all devices. This tutorial will bring in experts from member companies of the HSA Foundation to describe the Heterogeneous Systems Architecture and how it addresses the challenges of modern SOC devices.
Sun 8/25 Session Title Presenter Affiliation
9:00 AM Tutorial 1 HSA Overview Phil Rogers AMD
9:40 AM HSAIL Virtual Parallel ISA Ben Sander AMD
10:40 AM Break
11:00 AM HSA Memory Model Benedict Gaster Qualcomm
12:00 PM HSA Queuing Model Ian Bratt  ARM
1:00 PM Lunch
Fast Storage for Big Data Flash is emerging as a significant new storage technology for a wide range of storage requirements, spanning the industry from mobile devices to enterprise data centers. Its access time is 100X faster than traditional magnetic hard drives. However, exploitation of Flash is not straightforward as its physical characteristics introduce new requirements for the design of Flash-based storage components and fully integrated Flash-based storage systems. This tutorial will bring in experts from industry to talk about real systems,and the issues around exploiting flash memory technology in real system designs.
Sun 8/25 Session Title Presenter Affiliation
2:00 PM Tutorial 2 Introduction Tom McWilliams Bay Storage Technology
2:05 PM Flash’s Role in Big Data, Past Present, and Future Jim Handy Objective Analysis
2:30 PM NAND Technology Krishna Parat Intel
2:55 PM Delivering the Full Potential of PCIe Storage Amber Huffman Intel
3:20 PM Systems Level Controller Design Radoslav Danilak Skyera
3:45 PM Break
4:15 PM Systems Case Study Kevin Rowett Violin Memory
4:40 PM Flash in an Enterprise Storage Array: 10x Performance for Less Cost Than Disk Neil Vachharajani Pure Storage
5:05 PM Flash Trends: Challenges and Future John Davis Microsoft Research
5:30 PM Flash Adoption in the Enterprise David Flynn Primary Data
5:55 PM Wrap up Tom McWilliams Bay Storage Technology
6:00 PM Reception
7:00 PM End

 

Conference

Mon 8/26 Session Title Presenter Affiliation
9:10 AM Welcome Introductory Remarks
9:30 AM SoC 1 AMD’s Kabini APU SoC Dan Bouvier, Ben Bates, Walter Fry and Sreekanth Godey AMD
XBOX One Silicon John Sell and Pat O’Connor Microsoft
Clover Trail+ – Intel’s Next Atom SoC Smartphone Platform Mark Ewert, Prakash Iyer and Waldo Bastian Intel
11:00 AM Break
11:30 AM Keynote 1 DARPA, Director of Microsystems Technology Office “The Chip Design Game at the End of Moore’s Law” Dr. Robert Colwell DARPA
12:30 PM Lunch
1:30 PM Processors Next Generation POWER microprocessor Jeff Stuecheli IBM
IBM zEC12 Processor Subsystem: The Foundation for a Highly Reliable, High Performance Mainframe Symmetric Multiprocessor System Robert Sonnelitter IBM
2:30 PM Keynote 2 Google Glass Babak Parviz Google
3:30 PM Break
4:00 PM SoC 2 AMD’s “Richland” Client APU SoC Praveen Dongara, Lloyd Bircher and John Darilek AMD
A 50% Lower Power ARM Cortex CPU using DDC Transistors with Body Bias David Kidd SuVolta
5:00 PM Break
5:20 PM Interconnects Silicon Photonics Technology Platform for Integration of Optical IOs with ASICs Peter De Dobbelaere Luxtera
NetSpeed eNoC – a Quantum Leap in On-Chip Interconnect Design Sailesh Kumar NetSpeed
Integrating Rack Level Connectivity into a PCI Express Switch Jack Regula PLX Technology
6:50 PM Reception
7:50 PM End
Tue 8/27 Session Title Presenter Affiliation
8:30 AM FPGA Based Dataflow Dataflow architectures for 10Gbps line-rate key-value-stores Michaela Blott and Kees Vissers Xilinx
Going to the wire: The next generation financial risk management platform Ari Studnitzer (CME Group) and Oskar Mencer (Maxeler Technologies) Maxeler
An FPGA-based In-line Accelerator for Memcached Maysam Lavasani, Hari Angepat and Derek Chiou University of Texas
10:00 AM Break
10:30 AM Networking Serial Networking Memory, Bandwidth Engine, Breaks 4.5 Billion Access per Second Michael Miller Mosys
A 22nm High-Performance Flow Processor for 200Gb/s Software Defined Networking Gavin Stark and Sakir Sezer Netronome
11:30 AM Keynote 3 Intellectual Property Issues in the Computer and Electronics Industries Michael Brody, Vice-Chair, Intellectual Property Winston and Strawn
12:30 PM Lunch
1:30 PM Mobility Qualcomm Hexagon DSP: An Architecture Optimized for Mobile Multimedia and Communications Lucian Codrescu, Willie Anderson, Suresh Venkumanhanti, Mao Zeng, Erich Plondke, Chris Koob, Ajay Ingle, Rick Maule and Raj Talluri Qualcomm
Power Management Challenges in Wireless WAN SoCs Gunnar Bublitz Intel
5th Generation Touchscreen Controller for Mobile Phones and Tablets Milton Ribeiro and John Carey Cypress
3:00 PM Break
3:20 PM Processors 2 Hardware-level Thread Migration in a 110-core Shared-Memory Processor Mieszko Lis, Keun Sup Shim, Brandon Cho, Ilia Lebedev and Srinivas Devadas MIT
Intel 4th Generation Core Processor (Haswell) Srinivas Chennupaty, Per Hammarlund and Stephan Jourdan Intel
Microprocessors for Roots of Trust Kristopher Carver and Andras Moritz Bluerisc
4:50 PM Break
5:10 PM Processors 3 SPARC64 X+ : Fujitsu’s next generation processor for the UNIX servers Toshio Yoshida Fujitsu
SPARC M6: Oracle’s Next Generation Processor for Massively Scalable Symmetric Multiprocessor (SMP) Data Center Servers with Enterprise Class RAS Ali Vahidsafa and Sutikshan Bhutani Oracle
Bixby: the Scalability and Coherency Directory ASIC in Oracle’s M5/M6-32 Systems Thomas Wicki and Jurgen Schulz Oracle
6:40 PM Closing Remarks
6:50 PM End

 

Posters

Title Presenter
Designed and implemented a Programmable Network Interface fro high speed communications Mohamed Elbeshti from School of Engineering and Information Technology, Perth, WA, Australia
What a Fast FPU Means for Algorithms: A Story of Vector Mathematical Functions Marat Dukhan, College of Computing, Georgia Institute of Technology
A Scalable 3D Heterogeneous Multi-Core Processor with Inductive-Coupling ThruChip Interface Noriyuki Miura, Yusuke Koizumi, Eiichi Sasaki, Yasuhiro Take, Hiroki Matsutani, Tadahiro Kuroda and Hideharu Amano from Keio University; Ryuichi Sakamoto and Mitaro Namiki from Tokyo University of Agriculture and Technology; Kimiyoshi Usam from Shibaura Institute of Technology; Masaaki Kondo from University of Electro-Communications; Hiroshi Nakamura from The University of Tokyo, Japan
Exploring Manycore Multinode Systems for Irregular Applications with FPGA Prototyping Marco Ceriani and Gianluca Palermo from DEIB, Politecnico di Milano Milano, Italy; Simone Secchi from DIEE, Universita` di Cagliari Cagliari, Italy; Antonino Tumeo and Oreste Villa from Pacific Northwest National Laboratory Richland, WA, USA
ESESC: A Fast Integrated Architectural Simulator Ehsan K. Ardestani, Gabriel Southern, Jason Duong, Elnaz Ebrahimi and Jose Renau from UC Santa Cruz
Automatic Number Plate Recognition System on an ARM-DSP and FPGA Heterogeneous SoC Platforms Zoe Jeffrey, Reza Sotudeh and Aladdin Ariyaeeinia from University of Hertfordshire, UK; Xiaojun Zhai from University of Essex; Faycal Bensaali from Qatar University
Measuring the Gap between Programmable and Fixed-Function Accelerators: A Case Study on Speech Recognition Yunsup Lee, David Sheffield, Andrew Waterman, Michael Anderson, Kurt Keutzer and Krste Asanovic from UC Berkeley
The RISC-V Instruction Set Andrew Waterman, Yunsup Lee, David Patterson and Krste Asanovic from UC Berkeley

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