HC28 is over. Thanks to all our attendees, presenters, corporate sponsors, flint center and volunteers for making it happen.

Videos of talks available for attendees (same password given at conference and attendee emails) and for others in mid December.

(NOTE: Only attendees have access to tutorials, presentations and posters links below.)

Entire HC28 Tutorials, Conference & Posters:
(All files and links updated as of: Wed Aug 24 19:52:01 PDT 2016)

At A GlanceTutorialsConf. Day1Conf. Day2Posters
  • Sunday 8/21: Tutorials
    • 8:00 AM – 9:00 AM: Breakfast
    • 9:00 AM – 12:30 PM: Tutorial 1: Using Next-Generation Memory Technologies: DRAM and Beyond
    • 12:30 PM – 1:45 PM: Lunch
    • 1:45 PM – 5:00 PM: Tutorial 2: 3D Depth for Consumers: From Sensors to Apps
    • 5:00 PM – 6:00 PM: Reception
  • Monday 8/22: Conference Day 1
    • 8:30 AM – 9:30 PM: Breakfast
    • 9:30 AM – 9:45 PM: Introduction
    • 9:45 AM – 11:15 AM: GPUs and HPC Processors
    • 11:15 AM – 11:45 AM: Break
    • 11:45 AM – 12:45 PM: Processing on the Go: Mobile Devices
    • 12:45 PM – 2:15 PM: Lunch
    • 2:15 PM – 3:00 PM: Keynote 1: Mixed Reality
    • 3:00 PM – 4:00 PM: Energy-Efficient Computing: Low-Power SoCs
    • 4:00 PM – 4:30 PM: Break
    • 4:30 PM – 6:00 PM: Vision and Image Processing
    • 6:00 PM – 7:00 PM: Reception
  • Tuesday 8/23: Conference Day 2
    • 7:30 AM – 8:30 AM: Breakfast
    • 8:30 AM – 10:00 AM: Interconnects: Microns to Kilometers
    • 10:00 AM – 10:30 AM: Break
    • 10:30 AM – 12:00 PM: Emerging Embedded
    • 12:00 PM – 1:15 PM: Lunch
    • 1:15 PM – 2:15 PM: Keynote 2:  Are We There Yet? Silicon in Self-Driving Cars.
    • 2:15 PM – 3:15 PM: Many-Core Chips
    • 3:15 PM – 3:45 PM: Break
    • 3:45 PM – 5:15 PM: Dealing with Big Data
    • 5:15 PM – 5:45 PM: Break
    • 5:45 PM – 7:15 PM: High-Performance Processors
    • 7:15 PM – 7:30 PM: Closing Remarks


Sun 8/21 Tutorial Title Presenter Affiliation
8:00 AM Breakfast
Tutorial 1: Using Next-Generation Memory Technologies: DRAM and Beyond
Abstract: Memory technologies such as DRAM are rapidly changing from traditional interfaces and DRAM based devices to new interfaces, packages and device technologies.   This tutorial will describe new technologies from industry leading memory vendors  and show how they are used in new and emerging products and applications.  Presenters  include speakers from Micron, SK hynix, Samsung, Xilinx and  more…
9:00 AM Tutorial 1 Introduction Vidya Rajagopalan
9:10 AM Memory as We Approach a New Horizon Thomas Pawlowski Micron Technology
9:45 AM The Future of Graphic and Mobile Memory for New Applications Jin Kim Samsung
10:15 AM Break
10:35 AM The Era of High Bandwidth Memory Kevin Tran SK Hynix
11:10 AM HBM Package Integration: Technology Trends, Challenges and Applications Suresh Ramalingam Xilinx
11:45 AM Memory Technology and Applications Allen Rush AMD
12:15 PM Q & A Panel  All
12:30 PM Lunch
Tutorial 2: 3D Depth for Consumers: From Sensors to Apps
Abstract: 3D depth sensors are becoming increasingly ubiquitous, moving from robots and factories into cars and phones. Learn how sensor manufacturers, vision processing companies and application developers are enabling new depth – powered experiences for consumers.
1:45 PM Tutorial 2 Intro: 3D Sensors for the Rest of Us Larry Yang Google
2:00 PM VR and AR Anytime and Everywhere: Contributions of PMD Depth Sensing to an Evolving Ecosystem Bernd Buxbaum PMD Tech
2:30 PM “Speaking in Volumes”: Volumetric Data Acceleration for Dense SLAM David Moloney Movidius
3:00 PM Inuitive Breakthrough Solution for AR and VR Worlds Dor Zepeniuk Inuitive
3:30 PM Break
4:00 PM 3D Reconstruction for Consumer Mobile Devices Ivan Dryanovsk Google
4:30 PM Mobile 3D Capture for Professional Applications Rafael Spring DotProduct
5:00 PM Reception
6:00 PM End of Reception

Conference Day1

Mon 8/22 Session Title Presenter Affiliation
8:30 AM Breakfast
9:30 AM Welcome Introductory Remarks Stefan Rusu HC28 General Chair
9:45 AM GPUs & HPCs Bifrost, the new GPU architecture and its initial implementation, Mali-G71 Jem Davies ARM
Ultra-Performance Pascal GPU and NVLink Interconnect Denis Foley NVIDIA
ARMv8-A Next Generation Vector Architecture for HPC Nigel Stephens ARM
11:15 AM Break
11:45 AM Mobile Helio X20: The First Tri-Gear Mobile SoC with CorePilotTM 3.0 Technology David Lee Mediatek
Samsung’s Exynos-M1 CPU Brad Burgess Samsung
12:45 PM Lunch
2:15 PM Keynote 1 Mixed Reality Nick Baker Microsoft
Abstract: The Microsoft HoloLens is an untethered holographic computer that transforms ways we communicate, create, and explore. It creates high-definition, 3D holograms using advanced nano-optics and micro displays. These become part of the real world through on-board processing of data from an array of sensors continuously sampling the user’s environment. HoloLens combines all of the processing and components in a form factor that enables interaction with the real and the virtual in a most natural way.
3:00 PM Low Power SoC Design and Development of a an Ultra-Low Power x86 MCU Class SoCs Peter Barry Intel
NVIDIA Tegra-Next System-on-Chip Andi Skende NVIDIA
4:00 PM Break
4:30 PM Vision & Imaging From Model to FPGA: Software-Hardware Co-Design for Efficient Neural Network Acceleration Song Yao Deephi and Tsinghua University
The path to Embedded Vision and AI using a low power Vision DSP Yair Siegel CEVA
High Performance DSP for Vision, Imaging and Neural Networks Greg Efland Cadence
6:00 PM Reception
7:00 PM End of Reception

Conference Day2

Tue 8/23 Session Title Presenter Affiliation
7:30 AM Breakfast
8:30 AM Interconnects A 16nm 256-bit Wide 89.6GByte/s Total Bandwidth In-Package Interconnect with 0.3V Swing and 0.062pJ/bit Power in InFO Package Mu-Shan Lin TSMC
100Gbit/s, 120km, PAM 4 Based Switch to Switch, Layer 2 Silicon Photonics based Optical Interconnects for Datacenters Radhakrishnan Nagarajan, Sudeep Bhoja InPhi
Intel Omni-Path 4.8 Tbps Switch ASIC and Platform James Kunz Intel
10:00 AM Break
10:30 AM Emerging Embedded A “Zero-displacement” Active Ultrasonic Force Sensor for Mobile Applications Sam Sheng Sentons
Quantum Dot-Based Imagers for Multispectral Cameras and Sensors Emanuele Mandelli Invisage
Building the World’s First Super Active Suspension System Shakeel Avadhany Levant
12:00 PM Lunch
1:15 PM Keynote 2 Are We There Yet? Silicon in Self-Driving Cars. Daniel Rosenband Google
Abstract: Self-driving cars present a challenge in perceiving and interpreting information in a constantly changing environment. This keynote talk highlights these challenges and how silicon is a core enabler for self-driving compute and sensing technologies.

2:15 PM Multicore Research Piton: A 25-core Academic Manycore Processor Michael McKeown Princeton University
KiloCore: A 32 nm 1000-Processor Array Brent Bohnenstiehl UC Davis
 3:15 PM Break
 3:45 PM Dealing w/ Big Data Embedded Deep Neural Networks: “the cost of everything and the value of nothing” David Moloney Movidius
Software in Silicon in the Oracle SPARC M7 processor Kathirgamar Aingaran and David Lutz Oracle
SDA: Software-Defined Accelerator for General-Purpose Distributed Big Data Analysis System Jian Ouyang Baidu
5:15 PM Break
5:45 PM Processors Inside 6th generation Intel Core code named Skylake:: New Microarchitecture and Power Management Jack Doweck Intel
POWER9: Processor for the Cognitive Era Brian Thompto IBM
A New, High Performance x86 Core Design from AMD Michael Clark AMD
7:15 Closing Remarks
7:30 Conference Ends


Title Presenter
An Intelligent ADAS Processor with Real-Time Semi-Global Matching and Intention Prediction for 720p Stereo Vision Kyuho J. Lee, Kyeongryeol Bong, Changhyeon Kim, and Hoi-Jun Yoo of Korea Advanced Institute of Science and Technology (KAIST)
Deep Compression and EIE: Efficient Inference Engine on Compressed Deep Neural Network Song Han*, Xingyu Liu, Huizi Mao, Jing Pu, Ardavan Pedram,
Mark Horowitz, Bill Dally of Stanford
QORIQ® LS1012A:Big things in Small Packages: 64-Bit Core in a sub-10MM Package Ben Eckermann of NXP
A Dynamically Scheduled
Architecture for the Synthesis of Graph Methods
Marco Minutoli*, Vito Giovanni Castellana*, Antonino Tumeo*,
Marco Lattuada+, Fabrizio Ferrandi+ of *High Performance Computing, Pacific Northwest National Laboratory,
+DEIB, Politecnico di Milano
LiveSynth: Towards an Interactive Synthesis Flow Rafael Trapani Possignolo, Jose Renau of University of California, Santa Cruz
Modularizing the Microprocessor Core to Outperform Traditional Out-of-Order Tony Nowatzki Karthikeyan Sankaralingam of University of Wisconsin – Madison
Encoder Logic for Reducing Serial I/O Power in Sensors and Sensor Hubs Phillip Stanley-Marbell and Martin Rinard of MIT
Experiences Using a Novel Python-Based Hardware Modeling Framework for Computer Architecture Test Chips(paper)(slides) Christopher Torng of Cornell University
Reconfigure Your RTL with EFLX Cheng C. Wang and Dejan Marković of Flexlogix Technologies
Task Parallel Programming Model + Hardware Acceleration = Performance Advantage Tamer Dallou1, Cesar Divino Lucas2, Guido Araujo2, Lucas Morais2, Eduardo Ferreira Barbosa2, Michael Frank3, Richard Bagley3, Raj Sayana3 of 1 LG Electronics Technology Center Europe, 2University of Campinas, Brazil (Unicamp), 3LG Electronics Mobile Research, San Jose Lab
NOSQL Hardware appliance with Multiple Data Structure Yuta Tokusashi, Hiroki Matsutani of Keio University
AnyCore-1: A Comprehensively Adaptive 4-Way Superscalar Processor Rangeen Basu Roy Chowdhury, Anil K. Kannepalli, Eric Rotenberg of North Carolina State University
MvEcho – Acoustic Response Modelling for Auralisation(poster)(slides) Léonie Buckley, Sam Caulfield, David Moloney of Movidius Ltd.
Passive Dense Stereo Vision On The Myriad2 VPU Luca Puglia 1 Mircea Ionic ˘a 2 Giancarlo Raiconi 1 David Moloney 2 of 1 Universita’ degli Studi di Salerno, 2 Movidius Ltd.